SN74AUC74RGYRG4 [TI]

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET; 双上升沿触发的D型触发器具有清零和预设
SN74AUC74RGYRG4
型号: SN74AUC74RGYRG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
双上升沿触发的D型触发器具有清零和预设

触发器 锁存器 逻辑集成电路
文件: 总12页 (文件大小:560K)
中文:  中文翻译
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SN74AUC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES483AAUGUST 2003REVISED MARCH 2005  
FEATURES  
RGY PACKAGE  
(TOP VIEW)  
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Ioff Supports Partial-Power-Down Mode  
Operation  
1
14  
13  
12  
11  
10  
9
1D  
1CLK  
1PRE  
1Q  
2CLR  
2D  
2
3
4
5
6
Sub-1-V Operable  
Max tpd of 1.8 ns at 1.8 V  
2CLK  
2PRE  
2Q  
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
1Q  
7
8
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically  
for 1.65-V to 1.95-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for  
higher frequencies, the CLR input overrides the PRE input when they are both low.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
–40°C to 85°C  
QFN – RGY  
Tape and reel  
SN74AUC74RGYR  
MS74  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
D
X
X
H
L
Q
H
L
Q
L
H
L
X
X
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q0  
Q 0  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74AUC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES483AAUGUST 2003REVISED MARCH 2005  
LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC)  
PRE  
CLK  
C
C
C
TG  
C
C
C
C
D
TG  
TG  
TG  
C
C
C
CLR  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
MAX  
UNIT  
V
VCC  
VI  
Supply voltage range  
Input voltage range(2)  
Voltage range applied to any output in the high-impedance or power-off state(2)  
Output voltage range(2)  
3.6  
3.6  
3.6  
V
VO  
VO  
IIK  
V
–0.5 VCC + 0.5  
V
Input clamp current  
VI < 0  
–50  
–50  
±20  
±100  
47  
mA  
mA  
mA  
mA  
°C/W  
°C  
IOK  
IO  
Output clamp current  
VO < 0  
Continuous output current  
Continuous current through VCC or GND  
Package thermal impedance(3)  
Storage temperature range  
θJA  
Tstg  
–65  
150  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) The package thermal impedance is calculated in accordance with JESD 51-5.  
2
SN74AUC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES483AAUGUST 2003REVISED MARCH 2005  
Recommended Operating Conditions(1)  
MIN  
0.8  
MAX UNIT  
VCC  
Supply voltage  
2.7  
V
VCC = 0.8 V  
VCC  
VIH  
High-level input voltage  
VCC = 1.1 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 0.8 V  
0.65 × VCC  
1.7  
V
0
VIL  
Low-level input voltage  
VCC = 1.1 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
0.35 × VCC  
V
0.7  
3.6  
VCC  
–0.7  
–3  
–5  
–8  
–9  
0.7  
3
VI  
Input voltage  
0
0
V
V
VO  
Output voltage  
VCC = 0.8 V  
VCC = 1.1 V  
VCC = 1.4 V  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 0.8 V  
VCC = 1.1 V  
VCC = 1.4 V  
VCC = 1.65 V  
VCC = 2.3 V  
IOH  
High-level output current  
Low-level output current  
mA  
mA  
IOL  
5
8
9
t/v  
Input transition rise or fall rate  
Operating free-air temperature  
20  
85  
ns/V  
TA  
–40  
°C  
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
0.8 V to 2.7 V  
0.8 V  
MIN  
TYP(1) MAX UNIT  
IOH = –100 µA  
IOH = –0.7 mA  
IOH = –3 mA  
IOH = –5 mA  
IOH = –8 mA  
IOH = –9 mA  
IOL = 100 µA  
IOL = 0.7 mA  
IOL = 3 mA  
VCC – 0.1  
0.55  
1.1 V  
0.8  
1
VOH  
V
1.4 V  
1.65 V  
2.3 V  
1.2  
1.8  
0.8 V to 2.7 V  
0.8 V  
0.2  
0.25  
1.1 V  
0.3  
V
VOL  
IOL = 5 mA  
1.4 V  
0.4  
IOL = 8 mA  
1.65 V  
2.3 V  
0.45  
0.6  
IOL = 9 mA  
II  
VI = VCC or GND  
VI or VO = 2.7 V  
0 to 2.7 V  
0
±5  
±10  
10  
µA  
µA  
µA  
Ioff  
ICC  
VI = VCC or GND,  
VI = VCC or GND  
VI = VCC or GND  
IO = 0  
0.8 V to 2.7 V  
2.5 V  
D inputs  
2
Ci  
pF  
Control inputs  
2.5 V  
2.5  
(1) All typical values are at TA = 25°C.  
3
SN74AUC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES483AAUGUST 2003REVISED MARCH 2005  
Timing Requirements  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
VCC = 1.2 V  
± 0.1 V  
VCC = 1.5 V  
± 0.1 V  
VCC = 1.8 V  
± 0.15 V  
VCC = 2.5 V  
VCC = 0.8 V  
± 0.2 V  
MIN MAX  
350  
UNIT  
TYP  
100  
4.6  
6.6  
4.8  
2.3  
0
MIN MAX  
MIN MAX  
MIN  
MAX  
300  
fclock  
Clock frequency  
Pulse duration  
225  
250  
MHz  
CLK high or low  
CLR low  
1.3  
2
0.6  
1.5  
1.5  
0.6  
0
0.5  
1.5  
1.5  
0.6  
0
0.5  
tw  
1.5  
ns  
PRE low  
1.8  
1
1.5  
Data  
0.7  
Setup time before  
CLK↑  
tsu  
CLR inactive  
PRE inactive  
0
0.3  
ns  
ns  
0
0
0
0.2  
0.3  
0.3  
th  
Hold time, data after CLK↑  
2.1  
0.3  
0.3  
0.3  
Switching Characteristics  
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)  
VCC = 1.2 V VCC = 1.5 V  
± 0.1 V ± 0.1 V  
VCC = 1.8 V  
± 0.15 V  
VCC = 2.5 V  
± 0.2 V  
VCC = 0.8 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
TYP  
100  
9.5  
MIN MAX MIN MAX MIN TYP MAX MIN MAX  
fmax  
225  
1.3  
1.5  
1.6  
250  
0.7  
1.1  
1.1  
300  
0.5  
0.9  
0.9  
350  
0.5  
0.7  
0.7  
MHz  
CLK  
CLR  
PRE  
4
4.1  
4.7  
2.5  
2.9  
2.8  
1.2  
1.4  
1.4  
2.1  
2.4  
2.4  
1.4  
1.6  
1.6  
tpd  
Q or Q  
10.5  
12  
ns  
Switching Characteristics  
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)  
VCC = 1.8 V  
± 0.15 V  
VCC = 2.5 V  
± 0.2 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN TYP MAX MIN MAX  
fmax  
300  
1.2  
1.3  
1.3  
350  
1
MHz  
CLK  
CLR  
PRE  
1.9  
2.1  
2.1  
2.8  
3
2.2  
2.4  
2.5  
tpd  
Q or Q  
1.1  
1.1  
ns  
3.1  
Operating Characteristics  
TA = 25°C  
VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V  
TEST  
CONDITIONS  
PARAMETER  
UNIT  
TYP  
TYP  
TYP  
TYP  
TYP  
Power dissipation  
capacitance  
Cpd  
f = 10 MHz  
36  
36  
36  
37  
41  
pF  
4
SN74AUC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES483AAUGUST 2003REVISED MARCH 2005  
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
TEST  
/t  
PLH PHL  
S1  
Open  
2 × V  
S1  
Open  
GND  
R
L
t
t
From Output  
Under Test  
t
/t  
PLZ PZL  
CC  
/t  
GND  
PHZ PZH  
C
L
R
L
(see Note A)  
C
L
V
R
L
V
CC  
0.8 V  
2 k  
2 kΩ  
2 kΩ  
2 kΩ  
2 kΩ  
1 kΩ  
500 Ω  
0.1 V  
0.1 V  
0.1 V  
15 pF  
15 pF  
15 pF  
15 pF  
15 pF  
30 pF  
30 pF  
1.2 V ± 0.1 V  
1.5 V ± 0.1 V  
1.8 V ± 0.15 V  
2.5 V ± 0.2 V  
1.8 V ± 0.15 V  
2.5 V ± 0.2 V  
LOAD CIRCUIT  
0.15 V  
0.15 V  
0.15 V  
0.15 V  
V
CC  
Timing Input  
V /2  
CC  
0 V  
t
w
t
su  
t
h
V
CC  
V
CC  
V /2  
CC  
V /2  
CC  
Input  
V /2  
CC  
V /2  
CC  
Data Input  
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
V
CC  
CC  
Output  
Control  
V
CC  
/2  
V
CC  
/2  
V /2  
CC  
V /2  
CC  
Input  
0 V  
V
0 V  
t
t
t
PLZ  
t
t
PHL  
PZL  
PLH  
Output  
Waveform 1  
V
OH  
CC  
V
/2  
/2  
V
V
/2  
/2  
V
CC  
/2  
CC  
CC  
Output  
S1 at 2 × V  
V
OL  
+ V  
PHZ  
CC  
V
OL  
V
OL  
(see Note B)  
t
t
PZH  
t
PHL  
PLH  
/2  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
OH  
V
OH  
− V  
V
CC  
V
CC  
CC  
Output  
0 V  
V
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , slew rate 1 V/ns.  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
5
PACKAGE OPTION ADDENDUM  
www.ti.com  
21-May-2007  
PACKAGING INFORMATION  
Orderable Device  
SN74AUC74RGYR  
SN74AUC74RGYRG4  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
QFN  
RGY  
14  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
QFN  
RGY  
14  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
TAPE AND REEL BOX INFORMATION  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
(mm)  
SN74AUC74RGYR  
RGY  
14  
SITE 41  
180  
12  
3.85  
3.85  
1.35  
8
12  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
SN74AUC74RGYR  
RGY  
14  
SITE 41  
190.0  
212.7  
31.75  
Pack Materials-Page 2  
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TI

SN74AUC74_10

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
TI

SN74AUCH16244

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
TI

SN74AUCH16244DGGR

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
TI

SN74AUCH16244DGVR

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
TI

SN74AUCH16244GQLR

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
TI

SN74AUCH16244ZQLR

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
TI

SN74AUCH16244_07

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
TI

SN74AUCH16245DGGR

AUC SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, TSSOP-48
TI

SN74AUCH16245DGVR

AUC SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, TVSOP-48
TI

SN74AUCH16245GQLR

AUC SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PBGA56, VFBGA-56
TI