SN74AUCH16244 [TI]
16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS; 16位缓冲器/驱动器，具有三态输出
| 型号： | SN74AUCH16244 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总13页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
DGG OR DGV PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1
2
3
4
5
6
7
8
9
48
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
I
Supports Partial-Power-Down Mode
off
Operation
Sub 1-V Operable
V
42
V
Max t of 1.8 ns at 1.8 V
pd
CC
CC
2Y1
2Y2
41 2A1
40 2A2
39 GND
38 2A3
37 2A4
36 3A1
35 3A2
34 GND
33 3A3
32 3A4
Low Power Consumption, 20-µA Max I
±8-mA Output Drive at 1.8 V
CC
GND 10
2Y3 11
2Y4 12
3Y1 13
3Y2 14
GND 15
3Y3 16
3Y4 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
V
18
31
V
CC
CC
– 1000-V Charged-Device Model (C101)
4Y1 19
4Y2 20
GND 21
4Y3 22
4Y4 23
4OE 24
30 4A1
29 4A2
28 GND
27 4A3
26 4A4
25 3OE
description/ordering information
This 16-bit buffer/driver is operational at 0.8-V to
2.7-V V , but is designed specifically for 1.65-V
CC
to 1.95-V V
operation.
CC
The SN74AUCH16244 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
PACKAGE
TSSOP – DGG
A
Tape and reel
Tape and reel
Tape and reel
SN74AUCH16244DGGR
SN74AUCH16244DGVR
SN74AUCH16244GQLR
AUCH16244
MJ244
–40°C to 85°C TVSOP – DGV
VFBGA – GQL
MJ244
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
description/ordering information (continued)
Activebus-holdcircuitryholdsunusedorundriveninputsatavalidlogicstate. Useofpulluporpulldownresistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Y2
1Y4
2Y2
2Y4
3Y1
3Y3
4Y1
4Y3
4OE
NC
NC
NC
NC
2OE
1A2
1A4
2A2
2A4
3A1
3A3
4A1
4A3
3OE
A
B
C
D
1Y1
1Y3
2Y1
2Y3
3Y2
3Y4
4Y2
4Y4
NC
GND
GND
1A1
1A3
2A1
2A3
3A2
3A4
4A2
4A4
NC
V
CC
V
CC
GND
GND
E
F
G
H
J
GND
GND
V
CC
V
CC
G
H
J
GND
NC
GND
NC
K
NC – No internal connection
K
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
H
L
H
X
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
logic diagram (positive logic)
1
25
36
1OE
3OE
3A1
47
2
3
5
6
13
1A1
1Y1
1Y2
1Y3
1Y4
3Y1
46
35
33
32
14
1A2
3A2
3A3
3A4
3Y2
44
16
1A3
3Y3
43
17
1A4
3Y4
48
24
30
2OE
4OE
4A1
41
8
9
19
2A1
2Y1
2Y2
2Y3
2Y4
4Y1
40
29
27
26
20
2A2
4A2
4A3
4A4
4Y2
38
11
12
22
2A3
4Y3
37
23
2A4
4Y4
Pin numbers shown are for the DGG and DGV packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
0.8
2.7
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
V
CC
V
High-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 0.8 V
0.65 × V
V
V
CC
1.7
0
0.35 × V
0.7
V
IL
Low-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
CC
V
V
Input voltage
0
0
3.6
V
V
I
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
–0.7
–3
–5
–8
–9
0.7
3
= 1.1 V
I
High-level output current
Low-level output current
= 1.4 V
mA
mA
OH
OL
= 1.65 V
= 2.3 V
= 0.8 V
= 1.1 V
I
= 1.4 V
5
= 1.65 V
= 2.3 V
8
9
= 0.8 V
20
15
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
= 1.3 V
ns/V
= 1.6 V, 1.95 V, and 2.7 V
T
–40
°C
A
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
V –0.1
CC
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –0.7 mA
= –3 mA
= –5 mA
= –8 mA
= –9 mA
= 100 µA
= 0.7 mA
= 3 mA
0.8 V to 2.7 V
0.8 V
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
0.55
1.1 V
0.8
V
OH
V
1.4 V
1
1.65 V
2.3 V
1.2
1.8
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
0.4
V
OL
V
= 5 mA
1.4 V
= 8 mA
1.65 V
2.3 V
0.45
0.6
= 9 mA
I
I
A or OE inputs V = V
or GND
0 to 2.7 V
1.1 V
±5
µA
µA
I
I
CC
V = 0.35 V
I
10
15
V = 0.47 V
I
1.4 V
‡
BHL
V = 0.57 V
I
1.65 V
2.3 V
20
V = 0.7 V
I
40
V = 0.8 V
1.1 V
–10
–15
–20
–40
75
I
V = 0.9 V
I
1.4 V
§
I
I
I
µA
µA
µA
BHH
V = 1.07 V
I
1.65 V
2.3 V
V = 1.7 V
I
1.3 V
1.6 V
125
175
275
–75
¶
V = 0 to V
BHLO
I
CC
CC
1.95 V
2.7 V
1.3 V
1.6 V
–125
–175
–275
#
V = 0 to V
I
BHHO
1.95 V
2.7 V
I
I
I
V or V = 2.7 V
0
±10
±10
20
µA
µA
µA
pF
pF
off
I
O
V
O
= V or GND
CC
2.7 V
OZ
CC
V = V
or GND,
or GND
I
O
= 0
0.8 V to 2.7 V
2.5 V
I
CC
CC
C
C
V = V
I
3
4
4.5
7
i
V
O
= V or GND
CC
2.5 V
o
†
‡
All typical values are at T = 25°C.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
A
should be measured after lowering V to GND and
IN
IL
BHL
§
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
CC
± 0.1 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
V
CC
= 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN MAX
MIN MAX
MIN TYP MAX
MIN MAX
t
A
5.4
8
0.8
1
2.8
4.4
4.9
0.6
0.7
1
1.9
2.6
4.6
0.7
0.8
1.5
1.3
1.4
2.6
1.8
2.5
4
0.5
0.6
0.5
1.8
1.9
2
ns
ns
ns
Y
Y
Y
pd
t
en
OE
OE
t
12
1.9
dis
operating characteristics, T = 25°C
A
V
CC
= 0.8 V
V
CC
= 1.2 V
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
TEST
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
TYP
TYP
Outputs
enabled
21
1
22
1
23
1
25
1
30
1
Power
dissipation
capacitance
C
f = 10 MHz
pF
pd
Outputs
disabled
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
S1
TEST
/t
S1
R
L
From Output
Under Test
t
Open
PLH PHL
t
/t
2 × V
CC
GND
PLZ PZL
C
L
t
/t
R
PHZ PZH
L
(see Note A)
V
C
R
V
∆
L
L
CC
0.8 V
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
15 pF
15 pF
15 pF
30 pF
30 pF
LOAD CIRCUIT
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
0.1 V
0.15 V
0.15 V
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
V
V
V
OH
CC
V
/2
/2
V
V
/2
/2
V
CC
Output
CC
CC
V
V
+ V
∆
S1 at 2 × V
(see Note B)
OL
CC
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
74AUCH16244DGGRE4
74AUCH16244DGVRE4
SN74AUCH16244DGGR
SN74AUCH16244DGVR
TSSOP
DGG
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TSSOP
TVSOP
DGV
DGG
DGV
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AUCH16244GQLR
SN74AUCH16244ZQLR
ACTIVE
ACTIVE
VFBGA
VFBGA
GQL
ZQL
56
56
1000
TBD
SNPB
Level-1-240C-UNLIM
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74AUCH16373GQLR
IC AUC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PBGA56, VFBGA-56, Bus Driver/Transceiver
TI
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