SN74AUCH16373GQLR [TI]
IC AUC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PBGA56, VFBGA-56, Bus Driver/Transceiver;
| 型号： | SN74AUCH16373GQLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC AUC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PBGA56, VFBGA-56, Bus Driver/Transceiver 驱动 输出元件 逻辑集成电路 |
| 文件： | 总6页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
DGG OR DGV PACKAGE
(TOP VIEW)
D
D
Member of the Texas Instruments
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
2
3
D
I
Supports Partial-Power-Down Mode
off
4
Operation
5
D
D
D
D
D
Sub 1-V Operable
6
7
V
V
Max t of 2 ns at 1.8 V
pd
Low Power Consumption, 20-µA Max I
±8-mA Output Drive at 1.8 V
CC
CC
8
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
CC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
description/ordering information
This 16-bit transparent D-type latch is operational
at 0.8-V to 2.7-V V , but is designed specifically
CC
V
V
for 1.65-V to 1.95-V V
operation.
CC
CC
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2LE
The SN74AUCH16373 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
Thedevicecanbeusedastwo8-bitlatchesorone
16-bit latch. When the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
PACKAGE
TSSOP – DGG
A
Tape and reel
Tape and reel
Tape and reel
SN74AUCH16373DGGR
SN74AUCH16373DGVR
SN74AUCH16373GQLR
–40°C to 85°C TVSOP – DGV
VFBGA – GQL
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3–49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
description/ordering information (continued)
Activebus-holdcircuitryholdsunusedorundriveninputsatavalidlogicstate. Useofpulluporpulldownresistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
NC
NC
NC
1LE
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2LE
A
B
C
D
E
F
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
GND
GND
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
V
CC
V
CC
GND
GND
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC – No internal connection
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
LE
H
H
L
D
H
L
L
L
H
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
24
25
1OE
2OE
48
1LE
2LE
2D1
C1
C1
1D
2
13
1Q1
2Q1
47
36
1D1
1D
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
3–50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
0.8
2.7
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
V
CC
V
High-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 0.8 V
0.65 × V
V
V
CC
1.7
0
0.35 × V
0.7
V
IL
Low-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
CC
V
V
Input voltage
0
0
3.6
V
V
I
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
–0.7
–3
–5
–8
–9
0.7
3
I
High-level output current
Low-level output current
mA
mA
OH
OL
I
5
8
9
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
20
85
ns/V
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3–51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
V –0.1
CC
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –0.7 mA
= –3 mA
= –5 mA
= –8 mA
= –9 mA
= 100 µA
= 0.7 mA
= 3 mA
0.8 V to 2.7 V
0.8 V
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
0.55
1.1 V
0.8
V
OH
V
1.4 V
1
1.65 V
2.3 V
1.2
1.8
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
0.4
V
OL
V
= 5 mA
1.4 V
= 8 mA
1.65 V
2.3 V
0.45
0.6
= 9 mA
I
I
All inputs
V = V
or GND
0 to 2.7 V
1.1 V
±5
µA
µA
I
I
CC
V = 0.35 V
I
10
15
V = 0.47 V
I
1.4 V
‡
BHL
V = 0.57 V
I
1.65 V
2.3 V
20
V = 0.7 V
I
40
V = 0.8 V
1.1 V
–10
–15
–20
–40
75
I
V = 0.9 V
I
1.4 V
§
I
I
I
µA
µA
µA
BHH
V = 1.07 V
I
1.65 V
2.3 V
V = 1.7 V
I
1.3 V
1.6 V
125
175
275
–75
¶
V = 0 to V
BHLO
I
CC
CC
1.95 V
2.7 V
1.3 V
1.6 V
–125
–175
–275
#
V = 0 to V
I
BHHO
1.95 V
2.7 V
I
I
I
V or V = 2.7 V
0
±10
±10
20
µA
µA
µA
pF
pF
off
I
O
V
O
= V or GND
CC
2.7 V
OZ
CC
V = V
or GND,
or GND
I = 0
O
0.8 V to 2.7 V
2.5 V
I
CC
CC
C
C
V = V
I
i
V
O
= V or GND
CC
2.5 V
o
†
‡
All typical values are at T = 25°C.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
A
should be measured after lowering V to GND and
IN
IL
BHL
§
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
3–52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V = 1.2 V
CC
± 0.1 V
V = 1.5 V
CC
± 0.1 V
V = 1.8 V
CC
± 0.15 V
V = 2.5 V
CC
± 0.2 V
V
CC
= 0.8 V
UNIT
TYP
MIN MAX
MIN MAX
MIN MAX
MIN MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
CC
± 0.1 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
V
CC
= 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN MAX
MIN MAX
MIN TYP MAX
MIN MAX
D
t
ns
Q
pd
LE
OE
t
en
ns
ns
Q
Q
t
OE
dis
operating characteristics, T = 25°C
A
V
= 0.8 V
CC
TYP
V
= 1.2 V
CC
TYP
V
= 1.5 V
CC
TYP
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
TEST
PARAMETER
UNIT
CONDITIONS
Outputs
enabled
Power
dissipation
capacitance
C
f = 10 MHz
pF
pd
Outputs
disabled
3–53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
S1
TEST
/t
S1
R
L
From Output
Under Test
t
Open
PLH PHL
t
/t
2 × V
CC
GND
PLZ PZL
C
L
t
/t
R
PHZ PZH
L
(see Note A)
V
C
R
V
∆
L
L
CC
0.8 V
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
15 pF
15 pF
15 pF
30 pF
30 pF
LOAD CIRCUIT
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
0.1 V
0.15 V
0.15 V
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
V
V
V
OH
CC
V
/2
/2
V
V
/2
/2
V
CC
Output
CC
CC
V
V
+ V
∆
S1 at 2 × V
(see Note B)
OL
CC
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
3–54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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