SN74AUP1G04YZPR [TI]
LOW POWER SINGLE INVERTER GATE; 低功耗，单非门
| 型号： | SN74AUP1G04YZPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW POWER SINGLE INVERTER GATE |
| 文件： | 总12页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢃ
ꢊ ꢋꢌꢍꢆꢋ ꢌ ꢎꢏ ꢀꢐ ꢁꢈ ꢊ ꢎ ꢐꢁ ꢑꢎꢏ ꢒꢎ ꢏ ꢈ ꢄꢒꢎ
SCES571A − JUNE 2004 − REVISED APRIL 2005
D
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Low Static-Power Consumption;
D
D
D
D
D
D
Wide Operating V
Range of 0.8 V to 3.6 V
CC
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
I
= 0.9-µA Max
CC
Low Dynamic-Power Consumption;
= 4.1 pF Typical at 3.3 V
t
= 3.9 ns Max at 3.3 V
pd
C
pd
Suitable for Point-to-Point Applications
D
Low Input Capacitance; C = 1.5 pF Typical
i
Low Noise − Overshoot and Undershoot
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
<10% of V
CC
D
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D
D
I
Supports Partial-Power-Down Mode
off
Operation
Input Hysteresis Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
D
ESD Protection Exceeds 5000-V With
Human-Body Model
(V
= 250 mV Typical at 3.3 V)
hys
DBV, DCK, OR DRL PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
3 4
2
GND
A
DNU
Y
V
1
2
3
5
4
NC
A
GND
V
Y
CC
1 5
CC
DNU − Do not use
NC − No internal connection
description/ordering information
The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire V range
CC
of 0.8 V to 3.6 V resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
Switching Characteristics
Static-Power Consumption
Dynamic-Power Consumption
(pF)
100%
†
at 25 MHz
(µA)
3.5
3
100%
80%
60%
80%
2.5
2
Input
Output
60%
40%
3.3-V
3.3-V
†
Logic
1.5
1
†
Logic
40%
0.5
0
20%
0%
20%
0%
AUP
AUP
−0.5
10
15 20
Time − ns
0
5
25
35 40 45
30
†
Single, dual, and triple gates.
†
AUP1G08 data at C = 15 pF.
L
Figure 2. Excellent Signal Integrity
Figure 1. AUP−The Lowest-Power Family
This single inverter gate performs the Boolean function Y = A.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES571A − JUNE 2004 − REVISED APRIL 2005
description/ordering information (continued)
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Tape and reel SN74AUP1G04YEPR
_ _ _HC_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Tape and reel SN74AUP1G04YZPR
−40°C to 85°C
SOT (SOT-23) − DBV
Tape and reel SN74AUP1G04DBVR
Tape and reel SN74AUP1G04DCKR
H04_
HC_
SOT (SC-70) − DCK
SOT (SOT-533) − DRL
Reel of 4000
SN74AUP1G04DRLR
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1
identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
2
4
A
Y
2
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SCES571A − JUNE 2004 − REVISED APRIL 2005
§
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Output voltage range in the high or low state, V (see Note 1) . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
§
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SCES571A − JUNE 2004 − REVISED APRIL 2005
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
0.8
3.6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
V
CC
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 0.8 V
0.65 × V
CC
V
High-level input voltage
V
V
1.6
2
0
0.35 × V
0.7
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
CC
V
IL
Low-level input voltage
0.9
V
V
Input voltage
0
0
3.6
V
V
I
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65
−20
−1.1
−1.7
−1.9
−3.1
−4
µA
†
I
OH
High-level output current
mA
= 2.3 V
= 3 V
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
= 3 V
20
µA
1.1
1.7
1.9
3.1
4
†
I
OL
Low-level output current
mA
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
= 0.8 V to 3.6 V
200
85
ns/V
T
A
−40
°C
†
Defined by the signal integrity requirements and design goal priorities.
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCES571A − JUNE 2004 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25 °C
T = −40 °C TO 85 °C
A
A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
−0.1
TYP
MAX
MIN
V −0.1
CC
MAX
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= −20 µA
= −1.1 mA
= −1.7 mA
= −1.9 mA
= −2.3 mA
= −3.1 mA
= −2.7 mA
= −4 mA
0.8 V to 3.6 V
1.1 V
V
CC
OH
OH
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
OL
0.75 × V
1.11
1.32
2.05
1.9
0.7 × V
1.03
1.3
CC
CC
1.4 V
1.65 V
V
V
OH
1.97
1.85
2.67
2.55
2.3 V
3 V
2.72
2.6
= 20 µA
0.8 V to 3.6 V
1.1 V
0.1
0.3 × V
0.31
0.31
0.31
0.44
0.31
0.44
0.1
0.1
0.3 × V
0.37
0.35
0.33
0.45
0.33
0.45
0.5
= 1.1 mA
= 1.7 mA
= 1.9 mA
= 2.3 mA
= 3.1 mA
= 2.7 mA
= 4 mA
CC
CC
1.4 V
1.65 V
V
V
OL
2.3 V
3 V
I
I
A input
V = GND to 3.6 V
0 V to 3.6 V
0 V
µA
µA
µA
I
I
V or V = 0 V to 3.6 V
0.2
0.6
off
I
O
∆I
off
V or V = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
I
O
V = GND or
I
I
I
= 0 0.8 V to 3.6 V
0.5
40
0.9
50
µA
µA
CC
O
O
(V
CC
to 3.6 V)
∆I
CC
V = V −0.6 V
I
= 0
3.3 V
0 V
I
CC
1.5
1.5
2.5
C
C
V = V
or GND
pF
pF
i
I
CC
3.6 V
V
O
= GND
0 V
o
switching characteristics over recommended operating free-air temperature range, C = 5 pF
L
(unless otherwise noted) (see Figures 3 and 4)
T
= −40 °C
TO 85 °C
A
T
= 25 °C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
TYP
15.6
5.9
MAX
MIN
MAX
0.8 V
1.2 V 0.1 V
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
3.3
2.5
2.2
1.7
1.4
10.8
7
2.1
1.6
1.4
1.3
1.2
13.5
8.8
7
4.2
t
pd
A
ns
Y
3.4
5.9
4
2.5
4.9
3.9
2.1
3.2
5
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SCES571A − JUNE 2004 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range, C = 10 pF
L
(unless otherwise noted) (see Figures 3 and 4)
T
= −40 °C
TO 85 °C
A
T
= 25 °C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
TYP
17.7
6.9
5
MAX
MIN
MAX
0.8 V
1.2 V 0.1 V
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
3.9
3
12.2
8.1
6.9
4.6
3.8
3.1
2.5
2.1
1.7
1.5
15
9.9
7.9
5.6
4.5
t
pd
A
ns
Y
2.6
2.1
1.8
4
3
2.5
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figures 3 and 4)
T
= −40 °C
TO 85 °C
A
T
= 25 °C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
TYP
19.5
7.8
MAX
MIN
MAX
0.8 V
1.2 V 0.1 V
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
4.7
3.7
3.2
2.5
2.2
13
8.6
7.4
5.1
4.2
3.8
3.1
2.6
2.1
1.9
15.9
10.6
8.5
6.1
5
5.6
t
pd
A
ns
Y
4.6
3.5
2.9
switching characteristics over recommended operating free-air temperature range, C = 30 pF
L
(unless otherwise noted) (see Figures 3 and 4)
T
= −40 °C
TO 85 °C
A
T
= 25 °C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
TYP
25.4
10.4
7.6
MAX
MIN
MAX
0.8 V
1.2 V 0.1 V
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
6.8
5.3
4.6
3.6
3.2
16
10.8
9.2
6.1
4.8
4.1
3.3
2.9
19
12.9
10.5
7.6
t
pd
A
ns
Y
6.3
4.8
6.5
4
5.4
6.2
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
V
TYP
3.9
3.9
3.9
3.9
3.9
UNIT
CC
0.8 V
1.2 V 0.1 V
1.5 V 0.1 V
C
Power dissipation capacitance
f = 10 MHz
pF
pd
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
4.1
6
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SCES571A − JUNE 2004 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
From Output
Under Test
C
L
1 MΩ
(see Note A)
LOAD CIRCUIT
V = 1.2 V
CC
0.1 V
V = 1.5 V
CC
0.1 V
V = 1.8 V
CC
0.15 V
V = 2.5 V
CC
0.2 V
V = 3.3 V
CC
0.3 V
V
CC
= 0.8 V
C
5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF
L
V
M
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
t
w
V
CC
V
CC
/2
V
CC
/2
Input
V
I
0 V
V
M
V
M
Input
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
t
t
t
PHL
PLH
V
V
OH
V
CC
V
V
V
M
Output
M
Timing Input
Data Input
V
CC
/2
OL
0 V
t
PHL
PLH
t
t
h
su
V
V
OH
V
CC
V
M
M
Output
V
CC
/2
V
CC
/2
OL
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t /t = 3 ns.
O
r f
C. The outputs are measured one at a time, with one transition per measurement.
D. and t are the same as t
E. All parameters and waveforms are not applicable to all devices.
t
.
PLH
PHL pd
Figure 3. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉꢃ
ꢊ ꢋꢌꢍꢆ ꢋꢌꢎꢏ ꢀꢐ ꢁꢈ ꢊ ꢎ ꢐ ꢁꢑ ꢎ ꢏꢒꢎ ꢏ ꢈ ꢄꢒꢎ
SCES571A − JUNE 2004 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × V
CC
S1
5 kΩ
From Output
Under Test
GND
TEST
S1
t
/t
2 × V
GND
C
PLZ PZL
CC
L
5 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
V = 1.2 V
CC
0.1 V
V = 1.5 V
CC
0.1 V
V
= 1.8 V
V = 2.5 V
CC
0.2 V
V = 3.3 V
CC
0.3 V
CC
V
CC
= 0.8 V
0.15 V
C
5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF
/2 /2 /2 /2 /2 /2
L
V
M
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
V
CC
0.1 V
V
CC
0.1 V
V
CC
0.1 V
V
V
V
CC
0.3 V
I
CC
0.15 V
CC
0.15 V
V
∆
V
CC
Output
Control
V
CC
/2
V
CC
/2
0 V
t
t
PZL
PLZ
+ V
Output
Waveform 1
V
V
CC
V
/2
/2
CC
S1 at 2 × V
(see Note B)
V
V
CC
OL
∆
OL
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
− V
OH
∆
V
CC
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t /t = 3 ns.
O
r f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
t
and t
and t
are the same as t
.
dis
PLZ
PZL
PHZ
PZH
are the same as t
.
en
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2005
PACKAGING INFORMATION
Orderable Device
SN74AUP1G04DBVR
SN74AUP1G04DBVT
SN74AUP1G04DCKR
SN74AUP1G04DCKT
SN74AUP1G04DRLR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
5
3000
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
SOT-23
SC70
SC70
SOP
DBV
DCK
DCK
DRL
250
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
5
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-2/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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