SN74AVC16269DGGR [TI]
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS;
| 型号： | SN74AVC16269DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS 光电二极管 输出元件 逻辑集成电路 |
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SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
FEATURES
•
•
•
•
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
•
•
•
Member of the Texas Instruments Widebus™
Family
Ioff Supports Partial-Power-Down Mode
Operation
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DOC™ (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without Speed
Degradation
Package Options Include Plastic Thin Shrink
Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
•
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA
at 2.5-V VCC
DESCRIPTION
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry
Technology and Applications, literature number SCEA009.
3.2
T
A
= 25°C
T
A
= 25°C
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
CC
= 3.3 V
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
0
17
34
51
68
85 102 119 136 153 170
-160 -144 -128 -112 -96 -80 -64 -48 -32 -16
- Output Current - mA
0
I
- Output Current - mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
This 12-bit to 24-bit registered bus exchanger is operational at 1.2-V to 3.6-V VCC, but is designed specifically for
1.65-V to 3.6-V VCC operation.
The SN74AVC16269 is used in applications in which two separate ports must be multiplexed onto, or
demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous
DRAMs and high-speed microprocessors.
Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the
appropriate clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit
words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage
register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
DESCRIPTION (CONTINUED)
The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by
the active-low output enables (OEA, OEB1, OEB2).
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as
possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the
outputs cannot be determined prior to the arrival of the first clock pulse.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16269 is characterized for operation from –40°C to 85°C.
TERMINAL ASSIGNMENTS
DGG OR DGV PACKAGE
(TOP VIEW)
OEA
OEB1
2B3
GND
2B2
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEB2
CLKENA2
2B4
GND
2B5
2
3
4
5
2B1
6
2B6
V
CC
7
V
CC
A1
A2
A3
GND
A4
A5
8
2B7
2B8
2B9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
A6
A7
A8
A9
GND
A10
A11
A12
1B8
1B7
V
CC
V
CC
1B1
1B2
GND
1B3
NC
1B6
1B5
GND
1B4
CLKENA1
CLK
SEL
NC - No internal connection
2
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
FUNCTION TABLES
ABC
OUTPUT ENABLE
INPUTS
OUTPUTS
1B, 2B
CLK
OEA
OEB
H
A
Z
Z
↑
↑
↑
↑
H
H
L
Z
L
Active
Z
H
L
Active
Active
L
Active
A-TO-B STORAGE (OEB = L)
INPUTS
OUTPUTS
CLKENA1
CLKENA2
CLK
A
X
L
1B
2B
(1)
(1)
H
L
H
X
X
L
X
↑
↑
↑
↑
1B0
L
2B0
X
L
H
L
H
X
X
X
X
L
L
H
X
H
(1) Output level before the indicated steady-state input conditions were
established
B-TO-A STORAGE (OEA = L)
INPUTS
OUTPUT
A
CLK
SEL
H
1B
X
2B
X
(1)
X
X
↑
A0
(1)
L
X
X
A0
H
L
X
L
H
L
↑
H
H
X
X
↑
L
L
↑
L
X
H
H
(1) Output level before the indicated steady-state input conditions were
established
3
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
29
2
CLK
C1
1D
OEB1
C1
1D
56
30
55
28
1
OEB2
CLKENA1
CLKENA2
SEL
C1
1D
OEA
1D
1 of 12 Channels
C1
G1
C1
23
8
1B1
1
1
A1
1D
CE
C1
1D
6
2B1
CE
C1
1D
4
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
4.6
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
4.6
V
Voltage range applied to any input/output
VO
–0.5
–0.5
4.6
V
when the output is in the high-impedance or power-off state(2)
VO
IIK
Voltage range applied to any input/output when the output is in the high or low state(2)(3)
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through each VCC or GND
±50
±100
64
DGG package
DGV package
θJA
Package thermal impedance(4)
Storage temperature range
°C/W
°C
48
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
(4) The package thermal impedance is calculated in accordance with JESD 51.
5
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.4
1.2
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.2 V
VCC
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 1.2 V
0.65 × VCC
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
GND
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.35 × VCC
VIL
Low-level input voltage
0.35 × VCC
V
0.7
0.8
3.6
VCC
3.6
–2
–4
–8
–12
2
VI
Input voltage
0
0
0
V
V
Active state
VO
Output voltage
3-state
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 1.4 V to 3.6 V
IOHS
Static high-level output current(2)
Static low-level output current(2)
mA
mA
4
IOLS
8
12
5
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
TA
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 3.3-V VCC. See Figure 1 for VOL vs IOL and VOH
vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.
6
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.4 V to 3.6 V
1.4 V
MIN
VCC – 0.2
1.05
TYP(1)
MAX UNIT
IOHS = –100 µA
IOHS = –2 mA,
IOHS = –4 mA,
IOHS = –8 mA,
IOHS = –12 mA,
IOLS = 100 µA
IOLS = 2 mA,
VIH = 0.91 V
VOH
VIH = 1.07 V
VIH = 1.7 V
VIH = 2 V
1.65 V
2.3 V
1.2
V
1.75
3 V
2.3
1.4 V to 3.6 V
1.4 V
0.2
0.4
VIL = 0.49 V
VIL = 0.57 V
VIL = 0.7 V
VIL = 0.8 V
VOL
IOLS = 4 mA,
1.65 V
2.3 V
0.45
0.55
0.7
V
IOLS = 8 mA,
IOLS = 12 mA,
VI = VCC or GND
VI or VO = 3.6 V
VO = VCC or GND
VI = VCC or GND,
3 V
II
Control inputs
3.6 V
±2.5
±10
µA
µA
µA
µA
Ioff
0
(2)
IOZ
ICC
3.6 V
±12.5
40
IO = 0
3.6 V
2.5 V
3.5
3.5
8.5
8.5
Ci
Control inputs
A or B ports
VI = VCC or GND
VO = VCC or GND
pF
pF
3.3 V
2.5 V
Cio
3.3 V
(1) Typical values are measured at TA = 25°C.
(2) For I/O ports, the parameter IOZ includes the input leakage current.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5)
VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
VCC = 1.2 V
± 0.1 V
± 0.15 V
± 0.2 V
± 0.3 V
UNIT
TYP
MIN MAX MIN
MAX MIN MAX MIN
75 125
MAX
fclock Clock frequency
175
MHz
ns
tw
Pulse duration, CLK high or low
5.8
5
2.1
2.1
1.6
3.5
1.9
1.9
1.3
A data before CLK↑
B data before CLK↑
SEL before CLK↑
4.7
6.2
4.5
3.9
4.3
3.4
2.6
3
2.2
tsu
Setup time
ns
ns
CLKENA1 or CLKENA2 before
CLK↑
0.9
0.9
1
1.1
1.1
OE before CLK↑
A data after CLK↑
B data after CLK↑
SEL after CLK↑
5.4
1.9
0.4
1
5.3
2
2
1.2
0.5
0.4
1.6
1.1
0.6
0.3
1.1
1
1.3
1
0.7
0.4
th
Hold time
CLKENA1 or CLKENA2 after
CLK↑
2.6
0.4
2.2
0.4
1.4
0.4
1.1
0.5
1
OE after CLK↑
0.3
7
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5)
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.2 V
TYP
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
75
MAX
MIN
125
1.6
1.5
2.1
2
MAX
MIN
175
1.1
1
MAX
fmax
tpd
MHz
ns
B
A
B
A
B
A
13.5
11.6
16
3
2.6
3.5
3.2
4.9
3
9.5
7.4
2.5
2.2
2.4
2
6.7
5.8
8.5
6.7
8.5
6.7
4
3.5
4.8
4.4
4.8
3.6
3
2.7
3.8
3.4
3.7
3.4
CLK
CLK
CLK
12
1.5
1.4
1.3
1.7
ten
ns
ns
14.2
16
9.3
12.3
8.7
3.3
2.1
1.9
1.8
tdis
11.9
Switching Characteristics(1)
TA = 0°C to 85°C, CL = 0 pF
VCC = 3.3 V
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.4
MAX
B
A
2.4
2.1
tpd
CLK
ns
1.2
(1) Texas Instruments SPICE simulation data
Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
133
102
TYP
145
109
TYP
168
124
Outputs enabled
Outputs disabled
Power dissipation
capacitance
Cpd
CL = 0,
f = 10 MHz
pF
8
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × V
CC
S1
Open
GND
2 kΩ
From Output
Under Test
TEST
S1
t
pd
Open
C = 15 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
2 kΩ
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.1 V
CC
(see Note B)
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.1 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 2. Load Circuit and Voltage Waveforms
9
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × V
CC
S1
Open
GND
1 kΩ
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
1 kΩ
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 3. Load Circuit and Voltage Waveforms
10
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 4. Load Circuit and Voltage Waveforms
11
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES152G–DECEMBER 1998–REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × V
CC
TEST
S1
S1
500 Ω
Open
GND
From Output
Under Test
t
pd
Open
t
t
/t
2 × V
CC
GND
PLZ PZL
/t
C = 30 pF
(see Note A)
PHZ PZH
L
500 Ω
t
w
LOAD CIRCUIT
V
CC
Input
V /2
CC
V /2
CC
V
CC
Timing
Input
0 V
V
/2
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Data
Input
V /2
CC
V /2
CC
V
CC
Output
0 V
Control
(low-level
enabling)
V /2
CC
V /2
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
V
CC
V /2
CC
Input
V
OL
+ 0.3 V
V /2
CC
V /2
CC
S1 at 2 × V
CC
OL
0 V
(see Note B)
t
t
t
t
PHZ
PLH
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
V /2
CC
V /2
CC
V /2
CC
Output
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 5. Load Circuit and Voltage Waveforms
12
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
74AVC16269DGGRE4
74AVC16269DGGRG4
SN74AVC16269DGGR
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
56
56
56
2000
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AVC16269DGGR TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 56
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN74AVC16269DGGR
2000
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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