SN74AVC16334DGGR [TI]
16-Bit Universal Bus Driver With 3-State Outputs 48-TSSOP -40 to 85;
| 型号： | SN74AVC16334DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Universal Bus Driver With 3-State Outputs 48-TSSOP -40 to 85 总线驱动器 输出元件 |
| 文件： | 总12页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
Member of the Texas Instruments
Widebus Family
I
Supports Partial-Power-Down Mode
off
Operation
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
Ideal for Use in PC133 Registered DIMM
Applications
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I
and I
of
OH
OL
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
±24 mA at 2.5-V V
CC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V vs I and V
vs I
curves to illustrate the output impedance and drive capability of the
OL
OL
OH
OH
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
T
= 25°C
T
= 25°C
A
A
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
= 3.3 V
CC
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
= 2.5 V
CC
V
= 1.8 V
CC
V
= 3.3 V
V
= 2.5 V
CC
CC
V
= 1.8 V
CC
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16
– Output Current – mA
0
17
34
51
68
85 102 119 136 153 170
0
I
– Output Current – mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
This 16-bit universal bus driver is operational at 1.2-V to 3.6-V V , but is designed specifically for 1.65-V to
CC
3.6-V V
operation.
CC
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition
of CLK. When OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16334 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE
Y1
Y2
GND
Y3
Y4
CLK
A1
A2
GND
A3
A4
2
3
4
5
6
7
V
V
CC
Y5
CC
8
A5
A6
GND
A7
A8
9
Y6
GND
Y7
Y8
Y9
Y10
GND
Y11
Y12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A9
A10
GND
A11
A12
V
V
CC
CC
Y13
Y14
GND
Y15
Y16
NC
A13
A14
GND
A15
A16
LE
NC – No internal connection
FUNCTION TABLE
(each universal bus driver)
INPUTS
OUTPUT
Y
OE
H
L
LE
CLK
A
X
L
X
L
X
Z
L
X
L
L
X
H
L
H
L
L
H
H
H
↑
↑
L
H
X
H
†
Y
0
L
L or H
†
Output level before the indicated steady-state
input conditions were established
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
†
logic symbol
1
EN1
2C3
OE
48
CLK
25
C3
G2
LE
2
47
Y1
Y2
1
1
3D
A1
46
3
A2
44
5
Y3
A3
43
6
Y4
A4
41
8
Y5
A5
40
9
Y6
A6
38
11
12
13
14
16
17
19
20
22
23
Y7
A7
37
Y8
A8
36
Y9
A9
35
Y10
Y11
Y12
Y13
Y14
Y15
Y16
A10
33
A11
32
A12
30
A13
29
A14
27
A15
26
A16
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
48
CLK
25
LE
47
1D
C1
A1
2
Y1
CLK
To 15 Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
IK
I
Output clamp current, I
OK
O
O
Continuous current through each V
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
MIN
1.4
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
IH
Data retention only
1.2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2 V
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 1.2 V
0.65 × V
CC
V
High-level input voltage
0.65 × V
V
V
CC
1.7
2
GND
0.35 × V
0.35 × V
0.7
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
CC
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
0
3.6
V
V
I
Active state
3-state
V
CC
3.6
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
–2
–4
–8
†
I
Static high-level output current
mA
mA
OHS
OLS
–12
2
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
4
†
I
Static low-level output current
8
12
5
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
= 1.4 V to 3.6 V
ns/V
T
–40
85
°C
A
†
DynamicdrivecapabilityisequivalenttostandardoutputswithI
OH
andI of±24mAat2.5-VV .SeeFigure1forV vsI andV vs I
OL CC OL OL OH OH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
= –100 µA
MIN TYP
V –0.2
CC
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
1.4 V to 3.6 V
1.4 V
1.65 V
2.3 V
3 V
OHS
OHS
OHS
OHS
OHS
OLS
OLS
OLS
OLS
OLS
= –2 mA,
= –4 mA,
= –8 mA,
= –12 mA,
= 100 µA
= 2 mA,
V
V
V
V
= 0.91 V
= 1.07 V
= 1.7 V
= 2 V
1.05
1.2
IH
IH
IH
IH
V
V
OH
OL
1.75
2.3
1.4 V to 3.6 V
1.4 V
1.65 V
2.3 V
3 V
0.2
0.4
V
IL
V
IL
V
IL
V
IL
= 0.49 V
= 0.57 V
= 0.7 V
= 0.8 V
V
= 4 mA,
0.45
0.55
0.7
V
= 8 mA,
= 12 mA,
I
I
I
I
Control inputs
V = V or GND
CC
3.6 V
0
±2.5
±10
±10
40
µA
µA
µA
µA
I
I
V or V = 3.6 V
off
I
O
V
O
= V or GND
CC
3.6 V
3.6 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
OZ
CC
V = V
I
or GND,
I
O
= 0
CC
4
4
CLK input
Control inputs
Data inputs
Outputs
V = V
I
or GND
CC
4
C
V = V
or GND
or GND
pF
pF
i
I
CC
4
2.5
2.5
6.5
6.5
V = V
I
CC
C
V
O
= V
or GND
CC
o
†
Typical values are measured at T = 25°C.
A
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
= 1.2 V
MAX
CC
UNIT
MIN
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
150
150
150
MHz
ns
clock
LE low
3.3
3.3
0.7
0.9
1.2
3.3
3.3
0.7
0.9
1
3.3
3.3
0.7
0.9
1
Pulse
w
duration
CLK high or low
Data before CLK↑
1
1.5
2.7
0.8
1.4
1.6
Setup
time
t
su
CLK high
CLK low
ns
ns
Data
before LE↑
Hold
time
t
t
Data after CLK↑
1.3
1.1
0.9
0.8
0.7
h
CLK high
CLK low
2.2
2.4
1.9
1.8
1.7
1.6
1.5
1.4
1.5
1.3
ns
ns
Hold
time
Data
after LE↑
h
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
CC
= 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN
MAX
MIN
150
1.5
1.8
1.6
1.6
1.5
MAX
MIN
150
1
MAX
MIN
150
0.9
0.8
1
MAX
f
MHz
max
pd
A
5.3
7
1.2
2.2
1.9
2.4
2.1
6.2
9.7
4.9
7.5
6
3.2
4.9
3.7
6.7
5.3
2.5
4
t
LE
Y
1.5
1.1
1.5
1.2
ns
CLK
OE
OE
6
7.8
3.1
6.2
5.3
t
t
Y
Y
7.9
7.7
10.2
10.3
8.8
8.4
1
ns
ns
en
1
dis
†
switching characteristics, T = 0°C to 85°C, C = 0 pF
A
L
V
= 3.3 V
± 0.15 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
0.6
MAX
A
1.3
1.5
t
pd
Y
ns
CLK
0.7
†
Texas Instruments SPICE simulation data
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
CC
= 2.5 V
V = 3.3 V
CC
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
Outputs enabled
Outputs disabled
45
23
48
25
52
28
Power dissipation
capacitance
C
C
= 0,
L
f = 10 MHz
pF
pd
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
= 1.2 V AND 1.5 V ± 0.1 V
CC
2 × V
CC
Open
S1
2 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 15 pF
t
2 × V
CC
GND
L
PLZ PZL
2 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
CC
/2
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
+ 0.1 V
OL
CC
V
0 V
OL
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
– 0.1 V
V
CC
/2
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
= 1.8 V ± 0.15 V
CC
2 × V
CC
Open
GND
S1
1 kΩ
From Output
Under Test
TEST
S1
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
V
V
+ 0.15 V
V
S1 at 2 × V
(see Note B)
OL
CC
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 3. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
CC
Open
GND
S1
500 Ω
From Output
Under Test
TEST
S1
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
pd
Figure 4. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
2 × V
CC
TEST
S1
S1
500 Ω
Open
From Output
Under Test
t
Open
pd
GND
t
/t
2 × V
CC
GND
PLZ PZL
/t
t
C
= 30 pF
PHZ PZH
L
500 Ω
(see Note A)
t
LOAD CIRCUIT
w
V
CC
V
CC
/2
V
/2
CC
Input
V
CC
Timing
Input
0 V
V
/2
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Data
Input
Output
V
CC
V
CC
/2
V
CC
/2
Control
(low-level
enabling)
0 V
V
CC
/2
V
CC
/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
V
/2
/2
CC
Input
V
CC
/2
V
V
+ 0.3 V
S1 at 2 × V
(see Note B)
V
CC
/2
OL
CC
V
OL
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
/2
Output
Waveform 2
S1 at GND
V
OH
V
OH
– 0.3 V
OH
CC
V
CC
/2
Output
V
CC
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 5. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74AVC16374DGGE4
IC AVC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, TSSOP-48, Bus Driver/Transceiver
TI
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