SN74AVC16646 [TI]
16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS; 16位总线收发器和寄存器具有三态输出
| 型号： | SN74AVC16646 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS |
| 文件： | 总18页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
FEATURES
•
•
•
•
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
•
•
•
Member of the Texas Instruments Widebus™
Family
Ioff Supports Partial-Power-Down Mode
Operation
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DOC™ (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without Speed
Degradation
Package Options Include Plastic Thin Shrink
Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
•
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA
at 2.5-V VCC
DESCRIPTION
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry
Technology and Applications, literature number SCEA009.
3.2
T
A
= 25°C
T
A
= 25°C
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
CC
= 3.3 V
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
0
17
34
51
68
85 102 119 136 153 170
-160 -144 -128 -112 -96 -80 -64 -48 -32 -16
- Output Current - mA
0
I
- Output Current - mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
This 16-bit bus transceiver and register is operational at 1.2-V to 3.6-V VCC, but is designed specifically for
1.65-V to 3.6-V VCC operation.
The SN74AVC16646 can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is
clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 2
illustrates the four fundamental bus-management functions that can be performed with the SN74AVC16646.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
DESCRIPTION (CONTINUED)
The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the
transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the
isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function still is enabled and may be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16646 is characterized for operation from –40°C to 85°C.
TERMINAL ASSIGNMENTS
DGG OR DGV PACKAGE
(TOP VIEW)
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1CLKAB
1SAB
GND
1OE
2
1CLKBA
1SBA
GND
1B1
3
4
5
1A1
1A2
6
1B2
7
V
CC
V
CC
8
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
CC
V
CC
2A7
2A8
2B7
2B8
GND
GND
2SBA
2CLKBA
2OE
2SAB
2CLKAB
2DIR
2
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
FUNCTION TABLE
(EACH 8-BIT TRANSCEIVER/REGISTER)
INPUTS
DATA I/Os
OPERATION OR FUNCTION
OE
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1-A8
Input
B1-B8
Unspecified(1)
Input
X
X
H
H
L
↑
X
Store A, B unspecified(1)
Store B, A unspecified(1)
Store A and B data
X
X
↑
X
X
Unspecified(1)
X
↑
H or L
X
↑
H or L
X
X
X
Input
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
(1) The data-output functions may be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e.,
data at the bus terminals is stored on every low-to-high transition of the clock inputs.
3
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
DIR CLKAB CLKBA SAB
SBA
L
DIR
H
CLKAB CLKBA SAB
SBA
OE
L
OE
L
L
X
X
X
X
X
L
X
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
SBA
H
OE
X
OE
L
X
X
X
X
X
X
X
↑
X
↑
X
H or L
X
X
H
X
H
X
X
↑
L
H
H or L
X
↑
TRANSFER STORED DATA
TO A AND/OR B
STORAGE FROM
A, B, OR A AND B
Figure 2. Bus-Management Functions
4
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
LOGIC SYMBOL(1)
56
1
G3
1OE
1DIR
3 EN1 [BA]
3 EN2 [AB]
55
54
2
1CLKBA
1SBA
C4
G5
1CLKAB
1SAB
C6
3
G7
29
28
G10
2OE
2DIR
10 EN8 [BA]
10 EN9 [AB]
30
31
27
26
2CLKBA
2SBA
C11
G12
2CLKAB
2SAB
C13
G14
52
4D
2
1B1
≥1
5
5
1A1
1
5 1
6D
7
7
≥1
1
6
51
49
48
47
45
44
43
42
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B2
1B3
1B4
1B5
8
9
10
12
13
14
1B6
1B7
1B8
2B1
≥1
12 11D
12 1
15
2A1
8
13D 14 ≥1
9
1
14
16
17
19
20
21
23
24
41
40
38
37
36
34
33
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
5
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
56
1OE
1
1DIR
55
1CLKBA
1SBA
54
2
1CLKAB
3
1SAB
One of Eight Channels
1D
C1
5
1A1
52
1B1
1D
C1
To Seven Other Channels
29
2OE
28
30
2DIR
2CLKBA
2SBA
31
27
2CLKAB
26
2SAB
One of Eight Channels
1D
C1
15
2A1
42
2B1
1D
C1
To Seven Other Channels
6
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
4.6
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
4.6
V
Voltage range applied to any input/output
VO
–0.5
–0.5
4.6
V
when the output is in the high-impedance or power-off state(2)
VO
IIK
Voltage range applied to any input/output when the output is in the high or low state(2)(3)
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through each VCC or GND
±50
±100
64
DGG package
DGV package
θJA
Package thermal impedance(4)
Storage temperature range
°C/W
°C
48
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
(4) The package thermal impedance is calculated in accordance with JESD 51.
7
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
Recommended Operating Conditions(1)
MIN
1.2
MAX UNIT
VCC
Supply voltage
Operating
3.6
V
VCC = 1.2 V
VCC
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 1.2 V
0.65 × VCC
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
GND
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.35 × VCC
VIL
Low-level input voltage
0.35 × VCC
V
0.7
0.8
3.6
VCC
3.6
–2
–4
–8
–12
2
VI
Input voltage
0
0
0
V
V
Active state
VO
Output voltage
3-state
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 1.4 V to 3.6 V
IOHS
Static high-level output current(2)
Static low-level output current(2)
mA
mA
4
IOLS
8
12
5
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
TA
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 3.3-V VCC. See Figure 1 for VOL vs IOL and VOH
vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.
8
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
VCC
1.2 V to 3.6 V
1.4 V
MIN TYP(1)
VCC – 0.2
MAX UNIT
IOHS = –2 mA,
IOHS = –4 mA,
IOHS = –8 mA,
IOHS = –12 mA,
IOLS = 100 µA
IOLS = 2 mA,
VIH = 0.91 V
VIH = 1.07 V
VIH = 1.7 V
VIH = 2 V
1.05
1.2
VOH
1.65 V
2.3 V
V
1.75
2.3
3 V
1.2 V to 3.6 V
1.4 V
0.2
0.4
VIL = 0.49 V
VIL = 0.57 V
VIL = 0.7 V
VIL = 0.8 V
VOL
IOLS = 4 mA,
1.65 V
2.3 V
0.45
0.55
0.7
V
IOLS = 8 mA,
IOLS = 12 mA,
VI = VCC or GND
VI or VO = 3.6 V
VO = VCC or GND,
VI = VCC or GND,
3 V
II
Control inputs
3.6 V
±2.5
±10
µA
µA
µA
µA
Ioff
0
(2)
IOZ
ICC
VI = VCC
IO = 0
3.6 V
±12.5
40
3.6 V
2.5 V
3
3
CLK inputs
3.3 V
Ci
VI = VCC or GND
VO = VCC or GND
pF
pF
2.5 V
3.5
3.5
8
Control inputs
A or B ports
3.3 V
2.5 V
Cio
3.3 V
8
(1) Typical values are measured at TA = 25°C.
(2) For I/O ports, the parameter IOZ includes the input leakage current.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 through Figure 6)
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.2 V
MIN MAX
UNIT
MIN
MAX
MIN
MAX
150
MIN
MAX
250
MIN
MAX
350
fclock
tw
tsu
th
Clock frequency
MHz
ns
Pulse
CLKAB or CLKBA
3.3
1.2
0.8
2
0.9
0.6
1.4
0.8
0.6
duration
high or low
A before CLKAB↑ or
B before CLKBA↑
Setup time
Hold time
2.1
1.3
1.6
1
ns
ns
A after CLKAB↑ or
B after CLKBA↑
9
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 through Figure 6)
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.2 V
TYP
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
150
1.5
MAX
MIN
250
1.2
MAX
MIN
350
0.9
MAX
fmax
MHz
A or B
B or A
A or B
4.2
5.9
1.6
2.2
4.8
7.4
4.3
6.1
3.1
4
2.6
3.3
CLKAB or
CLKBA
tpd
1.9
1.3
1
ns
SAB or SBA
8.2
6.5
6.7
6.9
7.5
2.6
2.2
2.6
2.2
2.6
10
8
2.4
1.9
2.6
1.9
2.6
6.3
7
1.8
1.4
1.4
1.4
1.4
5.1
4.6
4.3
5
1.5
1.1
1.4
1.1
1.4
4
4
ten
tdis
ten
tdis
OE
OE
A or B
A or B
A or B
A or B
ns
ns
ns
ns
8
7.2
7.4
7.6
4.2
4.3
4.3
DIR
DIR
8.7
8.7
4.5
Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
62
TYP
73
TYP
120
34
Outputs enabled
Outputs disabled
Cpd
Power dissipation capacitance
CL = 0, f = 10 MHz
pF
25
29
10
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × V
CC
S1
Open
GND
2 kΩ
From Output
Under Test
TEST
S1
t
pd
Open
C = 15 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
2 kΩ
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.1 V
CC
(see Note B)
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.1 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 3. Load Circuit and Voltage Waveforms
11
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × V
CC
S1
Open
GND
1 kΩ
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
1 kΩ
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 4. Load Circuit and Voltage Waveforms
12
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 5. Load Circuit and Voltage Waveforms
13
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCES181F–DECEMBER 1998–REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × V
CC
TEST
S1
S1
500 Ω
Open
GND
From Output
Under Test
t
pd
Open
t
t
/t
2 × V
CC
GND
PLZ PZL
/t
C = 30 pF
(see Note A)
PHZ PZH
L
500 Ω
t
w
LOAD CIRCUIT
V
CC
Input
V /2
CC
V /2
CC
V
CC
Timing
Input
0 V
V
/2
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Data
Input
V /2
CC
V /2
CC
V
CC
Output
0 V
Control
(low-level
enabling)
V /2
CC
V /2
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
V
CC
V /2
CC
Input
V
OL
+ 0.3 V
V /2
CC
V /2
CC
S1 at 2 × V
CC
OL
0 V
(see Note B)
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
V /2
CC
V /2
CC
V /2
CC
Output
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 6. Load Circuit and Voltage Waveforms
14
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
74AVC16646DGGRE4
74AVC16646DGVRE4
SN74AVC16646DGGR
SN74AVC16646DGVR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TSSOP
TVSOP
DGV
DGG
DGV
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74AVC16646DGG
AVC SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PACKAGE-56
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