SN74AXCH4T245PWR [TI]

4 位双电源总线收发器 | PW | 16 | -40 to 125;


型号：	SN74AXCH4T245PWR
厂家：	TEXAS INSTRUMENTS
描述：	4 位双电源总线收发器 \| PW \| 16 \| -40 to 125 总线收发器
文件：	总39页 (文件大小：988K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SN74AXCH4T245

ZHCSJI7 –MARCH 2019

具有可配置电压转换、三态输出和总线保持输入的

SN74AXCH4T245 四位总线收发器

1 特性

有源总线保持电路会将未使用或未驱动的输入保持在有

效逻辑状态。不建议在总线保持电路上使用上拉或下拉

电阻器。如果 V_CCA或 V_CCB连上电源，则总线保持电

路分别在 A 或 B 输入端口上始终保持工作状态，与方

向控制或输出使能引脚的状态无关。

•

完全可配置的双电源轨设计可允许各个端口在

0.65V 至 3.6V 的电源电压范围内运行

•

总线保持数据输入消除了对外部上拉或下拉电阻器

的需求

•

工作温度范围 -40°C 至 +125°C

多向控制引脚，支持同步升降转换

无干扰电源定序

为了确保电平转换器 I/O 在加电或断电期间的高阻抗状

态，xOE 引脚应通过一个上拉电阻器连接至 V_CCA

。

从 1.8V 转换到 3.3V 时，支持高达 380Mbps 的转

换速率

该器件完全适用于使用 I_off电流的局部掉电应用。当

器件掉电时，I_off保护电路可确保不从输入/输出或偏置

到特定电压的组合 I/O 获取或向其提供多余电流。

•

V_CC隔离特性

I_off支持局部断电模式运行

V_CC隔离特性可确保当 V_CCA或 V_CCB低于 100mV

兼容 AVC 系列电平转换器

时，所有 I/O 端口均禁用其输出并进入高阻抗状态。

闩锁性能超过 100mA，符合 JESD 78 II 类规范

静电放电 (ESD) 保护性能超过 JESD 22 规范要求

无干扰电源定序使电源轨能以任何顺序打开或关断，从

而提供强大的电源定序性能。

–

8000V 人体放电模型

1000V 充电器件模型

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

5.00mm x 4.40mm

2.60mm x 1.80mm

2 应用

SN74AXCH4T245PW TSSOP (16)

SN74AXCH4T245RSV UQFN (16)

•

企业与通信

工业

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

个人电子产品

无线基础设施

楼宇自动化

功能方框图

One of Two Transceiver Pairs

3 说明

V_CCA

V_CCB

SN74AXCH4T245 是一款使用两个独立可配置电源轨

的四位同相总线收发器。V_CCA和 V_CCB电源电压低至

0.65V 时，该器件可正常工作。A 端口用于跟踪

xDIR

xOE

_CCA，该端口可支持 0.65V 至 3.6V 范围内的任何电

Bus-Hold

源电压。B 端口用于跟踪 V_CCB，该端口可支持 0.65V

至 3.6V 范围内的任何电源电压。SN74AXCH4T245

器件与单电源系统兼容。

xB1

xB2

xA1

xA2

Bus-Hold

SN74AXCH4T245 器件旨在实现数据总线间的异步通

信，根据方向控制输入（1DIR 和 2DIR）的逻辑电

平，将数据从 A 总线传输至 B 总线，或将数据从 B 总

线传输至 A 总线。输出使能输入（1OE 和 2OE）可用

于禁用输出，从而有效隔离总线。所有控制引脚

（xDIR 和 xOE）以 V_CCA为基准。

Bus-Hold

Note: Bus-hold circuits are only present for data inputs, not control inputs

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCES878

SN74AXCH4T245

ZHCSJI7 –MARCH 2019

www.ti.com.cn

7.1 Load Circuit and Voltage Waveforms ..................... 19

Detailed Description ............................................ 21

8.1 Overview ................................................................. 21

8.2 Functional Block Diagram ....................................... 21

8.3 Feature Description................................................. 21

8.4 Device Functional Modes........................................ 23

Application and Implementation ........................ 24

9.1 Application Information............................................ 24

9.2 Typical Application ................................................. 24

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics, V_CCA= 0.7 ± 0.05 V........ 8

6.7 Switching Characteristics, V_CCA= 0.8 ± 0.04 V........ 9

6.8 Switching Characteristics, V_CCA= 0.9 ± 0.045 V.... 10

6.9 Switching Characteristics, V_CCA= 1.2 ± 0.1 V........ 11

6.10 Switching Characteristics, V_CCA= 1.5 ± 0.1 V...... 12

6.11 Switching Characteristics, V_CCA= 1.8 ± 0.15 V.... 13

6.12 Switching Characteristics, V_CCA= 2.5 ± 0.2 V...... 14

6.13 Switching Characteristics, V_CCA= 3.3 ± 0.3 V...... 15

6.14 Operating Characteristics: T_A= 25°C ................... 16

6.15 Typical Characteristics.......................................... 18

Parameter Measurement Information ................ 19

10 Power Supply Recommendations ..................... 26

11 Layout................................................................... 26

11.1 Layout Guidelines ................................................. 26

11.2 Layout Example .................................................... 26

12 器件和文档支持 ..................................................... 27

12.1 相关文档ꢀ ........................................................... 27

12.2 接收文档更新通知 ................................................. 27

12.3 社区资源................................................................ 27

12.4 商标....................................................................... 27

12.5 静电放电警告......................................................... 27

12.6 术语表 ................................................................... 27

13 机械、封装和可订购信息....................................... 28

4 修订历史记录

日期

修订版本

说明

2019 年 3 月

初始发行版。

SN74AXCH4T245

www.ti.com.cn

ZHCSJI7 –MARCH 2019

5 Pin Configuration and Functions

PW Package

16-Pin TSSOP

Top View

RSV Package

16-Pin UQFN

Transparent Top View

V_CCA

1DIR

2DIR

1A1

V_CCB

1OE

2OE

1B1

1B2

2B1

2B2

GND

16 15 14 13

2B2

GND

2A2

1OE

V_CCB

1A2

V_CCA

2A1

1DIR

2A2

GND

Pin Functions

NO.

TYPE

DESCRIPTION

NAME

RSV

1A1

1A2

1B1

1B2

1DIR

I/O

Input/output 1A1. Referenced to V_CCA

Input/output 1A2. Referenced to V_CCA

Input/output 1B1. Referenced to V_CCB

Input/output 1B2. Referenced to V_CCB

Direction-control input for ‘1’ ports

Tri-state output-mode enable. Pull OE high to place ‘1’ outputs in tri-state

mode. Referenced to V_CCA

1OE

2A1

2A2

2B1

2B2

2DIR

I/O

Input/output 2A1. Referenced to V_CCA

Input/output 2A2. Referenced to V_CCA

Input/output 2B1. Referenced to V_CCB

Input/output 2B2. Referenced to V_CCB

Direction-control input for ‘2’ ports

Tri-state output-mode enable. Pull OE high to place ‘2’ outputs in tri-state

2OE

mode. Referenced to V_CCA

GND

V_CCA

V_CCB

8, 9

10, 11

—

Ground

A-port power supply voltage. 0.65 V ≤ V_CCA≤ 3.6 V

B-port power supply voltage. 0.65 V ≤ V_CCB≤ 3.6 V

SN74AXCH4T245

ZHCSJI7 –MARCH 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

UNIT

MIN

MAX

V_CCASupply voltage A

V_CCBSupply voltage B

–0.5

4.2

I/O Ports (A Port)

I/O Ports (B Port)

Control Inputs

A Port

V_I

Input Voltage⁽²⁾

V_O

Voltage applied to any output in the high-impedance or power-off state⁽²⁾

Voltage applied to any output in the high or low state⁽²⁾⁽³⁾

B Port

A Port

–0.5 V_CCA+ 0.2

–0.5 V_CCB+ 0.2

–50

B Port

I_IK

I_OK

I_O

Input clamp current

V_I< 0

Output clamp current

V_O< 0

–50

Continuous output current

Continuous current through V_CCor GND

Junction Temperature

–50

50 mA

–100

100 mA

T_j

150

°C

T_stg

Storage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6.2 ESD Ratings

VALUE

±8000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

SN74AXCH4T245

www.ti.com.cn

ZHCSJI7 –MARCH 2019

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^(1)(2)(3)

MIN

0.65

MAX UNIT

V_CCA

V_CCB

Supply voltage A

Supply voltage B

3.6

0.65

V_CCI= 0.65 V - 0.75 V

V_CCI= 0.76 V - 1 V

V_CCI= 1.1 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3 V - 3.6 V

V_CCIx 0.70

V_CCIx 0.65

1.6

Data Inputs

V_CCIx 0.65

V_CCAx 0.70

V_CCAx 0.65

1.6

V_IH

High-level input voltage

V_CCA= 0.65 V - 0.75 V

V_CCA= 0.76 V - 1 V

V_CCA= 1.1 V - 1.95 V

V_CCA= 2.3 V - 2.7 V

V_CCA= 3 V - 3.6 V

V_CCI= 0.65 V - 0.75 V

V_CCI= 0.76 V - 1 V

V_CCI= 1.1 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3 V - 3.6 V

Control Inputs(xDIR, xOE)

Referenced to V_CCA

V_CCAx 0.65

V_CCIx 0.30

V_CCIx 0.35

0.7

Data Inputs

0.8

V_IL

Low-level input voltage

V_CCA= 0.65 V - 0.75 V

V_CCA= 0.76 V - 1 V

V_CCA= 1.1 V - 1.95 V

V_CCA= 2.3 V - 2.7 V

V_CCA= 3 V - 3.6 V

V_CCAx 0.30

V_CCAx 0.35

0.7

Control Inputs(xDIR, xOE)

Referenced to V_CCA

0.8

(3)

V_I

Input voltage

3.6

Active State

Tri-State

V_CCO

V_O

Output voltage

3.6

Δt/Δv⁽²⁾Input transition rise and fall time

10 ns/V

125 °C

T_AOperating free-air temperature

–40

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

(3) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, SCBA004.

6.4 Thermal Information

SN74AXCH4T245

THERMAL METRIC⁽¹⁾

PW (TSSOP)

16 PINS

126.9

RSV (UQFN)

16 PINS

130.1

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

49.3

70.3

74.3

57.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

8.1

4.6

ψ_JB

73.4

55.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

SN74AXCH4T245

ZHCSJI7 –MARCH 2019

www.ti.com.cn

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

(1)(2)

Operating free-air temperature (T_A)

-40°C to 85°C -40°C to 125°C

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

UNIT

MIN TYP⁽³⁾

MAX

MIN TYP⁽³⁾

MAX

V_CCO

– 0.1

V_CCO

– 0.1

I_OH= -100 µA

0.7 V - 3.6 V 0.7 V - 3.6 V

I_OH= -50 µA

I_OH= -200 µA

I_OH= -500 µA

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.55

0.58

0.65

0.85

1.05

1.2

0.55

0.58

0.65

0.85

1.05

1.2

High-level

output

voltage

V_OH

V_I= V_IH

I_OH= -3 mA

I_OH= -6 mA

I_OH= -8 mA

I_OH= -9 mA

I_OH= -12 mA

I_OL= 100 µA

I_OL= 50 µA

I_OL= 200 µA

I_OL= 500 µA

V_I= V_ILI_OL= 3 mA

I_OL= 6 mA

1.75

2.3

1.75

2.3

0.7 V - 3.6 V 0.7 V - 3.6 V

0.1

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.18

0.2

0.18

0.2

Low-level

output

voltage

V_OL

0.25

0.35

0.45

0.55

0.7

0.25

0.35

0.45

0.55

0.7

I_OL= 8 mA

I_OL= 9 mA

I_OL= 12 mA

V_I= 0.20 V

V_I= 0.23 V

V_I= 0.26 V

V_I= 0.39 V

V_I= 0.49 V

V_I= 0.58 V

V_I= 0.7 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

Bus-hold low

sustaining

current (Port

I_BHL

µA

A or Port B)

(4)

V_I= 0.8 V

145

–4

135

–4

V_I= 0.20 V

V_I= 0.23 V

V_I= 0.26 V

V_I= 0.39 V

V_I= 0.49 V

V_I= 0.58 V

V_I= 0.7 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

–8

–7

Bus-hold

high

sustaining

–10

–20

–40

–55

–90

–145

–10

–20

–30

–45

–80

–135

I_BHH

µA

current (Port

A or Port B)

(5)

V_I= 0.8 V

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

(3) All typical data is taken at 25°C.

(4) The bus-hold circuit can sink at least the minimum low sustaining current at V_ILmax. I_BHLshould be measured after lowering V_INto GND

and then raising it to V_ILmax.

(5) The bus-hold circuit can source at least the minimum high sustaining current at V_IHmin. I_BHHshould be measured after raising V_INto

VCC and then lowering it to V_IHmin.

SN74AXCH4T245

www.ti.com.cn

ZHCSJI7 –MARCH 2019

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

Operating free-air temperature (T_A)

-40°C to 85°C -40°C to 125°C

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

UNIT

MIN TYP⁽³⁾

MAX

MIN TYP⁽³⁾

MAX

0.75 V

0.84 V

0.95 V

1.3 V

0.84 V

0.95 V

1.3 V

Bus-hold low

overdrive

I_BHLOcurrent (Port V_I= 0 to V_CC

105

µA

1.6 V

150

A or Port B)

(6)

1.95 V

2.7 V

1.95 V

2.7 V

205

335

3.6 V

480

0.75 V

0.84 V

0.95 V

1.3 V

0.75 V

0.84 V

0.95 V

1.3 V

–40

–50

Bus-hold

high

overdrive

–65

–105

–150

–205

–335

–480

–105

–150

–205

–335

–480

I_BHHO

V_I= 0 to VCC

µA

current (Port

1.6 V

A or Port B)

(7)

1.95 V

2.7 V

1.95 V

2.7 V

3.6 V

Control inputs (xDIR,

xOE): V_I= V_CCAor GND

0.65 V- 3.6 V 0.65 V- 3.6 V

–0.5

–4

0.5

–1

–8

µA

Input leakage

current

I_I

Data Inputs (xAx, xBx)

V_I= V_CCIor GND

A Port: V_Ior V_O= 0 V -

3.6 V

0 V

0 V - 3.6 V

0 V

–8

–12

Partial power

down current

I_off

µA

B Port: V_Ior V_O= 0 V -

3.6 V

0 V - 3.6 V

–8

A or B Port

V_I= V_CCIor GND, V_O

V_CCOor GND, OE = V_IH

Tri-state

output

current

I_OZ

3.6 V

–4

–2

–8

µA

(8)

0.65 V- 3.6 V 0.65 V- 3.6 V

V_I=

V_CCAsupply

current

I_CCA

V_CCIor I_O= 0

GND

0 V

3.6 V

0 V

–12

3.6 V

0.65 V- 3.6 V 0.65 V- 3.6 V

V_I=

V_CCBsupply

current

I_CCB

V_CCIor I_O= 0

GND

0 V

3.6 V

0 V

µA

3.6 V

–2

–12

Combined

supply

current

V_I=

I_CCA

I_CCB

V_CCIor I_O= 0

GND

0.65 V- 3.6 V 0.65 V- 3.6 V

µA

Control Input

Capacitance

C_i

V_I= 3.3 V or GND

3.3 V

4.5

7.4

4.5

7.4

OE = V_CCA, V_O= 1.65V

DC +1 MHz -16 dBm sine 3.3 V

wave

Data I/O

Capacitance

C_io

(6) An external driver must source at least I_BHLOto switch this node from low to high.

(7) An external driver must sink at least I_BHHOto switch this node from high to low.

(8) For I/O ports, the parameter I_OZincludes the input leakage current.

SN74AXCH4T245

ZHCSJI7 –MARCH 2019

www.ti.com.cn

6.6 Switching Characteristics, V_CCA= 0.7 ± 0.05 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

161

159

158

243

292

0.5

109

134

159

122

243

192

0.5

181

Propagation

delay

t_pd

112

159

102

243

134

159

125

243

148

t_disDisable time

243

t_enEnable time

SN74AXCH4T245

www.ti.com.cn

ZHCSJI7 –MARCH 2019

6.7 Switching Characteristics, V_CCA= 0.8 ± 0.04 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

134

109

110

147

143

253

0.5

Propagation

delay

t_pd

110

111

143

164

110

t_disDisable time

143

117

143

t_enEnable time

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6.8 Switching Characteristics, V_CCA= 0.9 ± 0.045 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

112

0.5

Propagation

delay

t_pd

t_disDisable time

141

106

t_enEnable time

229

149

107

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6.9 Switching Characteristics, V_CCA= 1.2 ± 0.1 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

t_disDisable time

133

134

100

t_enEnable time

168

109

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6.10 Switching Characteristics, V_CCA= 1.5 ± 0.1 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

t_disDisable time

131

132

t_enEnable time

109

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6.11 Switching Characteristics, V_CCA= 1.8 ± 0.15 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

t_disDisable time

129

131

t_enEnable time

102

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6.12 Switching Characteristics, V_CCA= 2.5 ± 0.2 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

t_disDisable time

128

129

t_enEnable time

120

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6.13 Switching Characteristics, V_CCA= 3.3 ± 0.3 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Condtions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

182

t_disDisable time

142

t_enEnable time

194

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MAX UNIT

6.14 Operating Characteristics: T_A= 25°C

PARAMETER

TEST CONDITIONS

V_CCA

0.7 V

V_CCB

0.7 V

MIN

TYP

2.2

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

2.3

Power Dissipation Capacitance

per transceiver (A to B: outputs

enabled)

2.3

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

2.2

2.5

2.6

1.5

1.7

Power Dissipation Capacitance

per transceiver (A to B: outputs

disabled)

1.7

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.5

1.8

2.1

C_pdA

12.6

12.4

12.8

13.3

14.6

18.0

21.1

1.1

Power Dissipation Capacitance

per transceiver (B to A: outputs

enabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.1

1.0

Power Dissipation Capacitance

per transceiver (B to A: outputs

disabled)

1.0

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.0

0.9

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Operating Characteristics: T_A= 25°C (continued)

PARAMETER

TEST CONDITIONS

V_CCA

0.7 V

V_CCB

0.7 V

MIN

TYP

MAX UNIT

12.6

12.4

12.8

13.3

14.6

17.8

21.0

1.1

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

Power Dissipation Capacitance

per transceiver (A to B: outputs

enabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.1

1.0

Power Dissipation Capacitance

per transceiver (A to B: outputs

disabled)

1.0

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.0

0.9

C_pdB

2.2

Power Dissipation Capacitance

per transceiver (B to A: outputs

enabled)

2.0

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

2.0

1.9

2.0

2.6

1.6

1.5

1.6

Power Dissipation Capacitance

per transceiver (B to A: outputs

disabled)

1.4

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.3

1.2

1.4

1.9

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6.15 Typical Characteristics

3.4

3.2

1.25

1.2

V_CC= 1.8V

V_CC= 2.5V

V_CC= 3.3V

1.15

1.1

1.05

2.8

2.6

2.4

2.2

0.95

0.9

0.85

0.8

0.75

0.7

1.8

1.6

1.4

0.65

0.6

V_CC= 0.7V

V_CC= 1.2V

0.55

0.5

1.5

2.5

3.5

4.5

I_OH(mA)

D001

图 1. Typical (T_A=25°C) Output High Voltage (V_OH) vs Source

Current (I_OH

图 2. Typical (T_A=25°C) Output High Voltage (V_OH) vs Source

Current (I_OH

)

700

650

600

550

500

450

400

350

300

250

200

150

100

220

200

180

160

140

120

100

V_CC= 1.8V

V_CC= 2.5V

V_CC= 3.3V

V_CC= 0.7V

V_CC= 1.2V

-50

0.5

1.5

2.5

3.5

4.5

I_OL(mA)

D001

图 3. Typical (T_A=25°C) Output High Voltage (V_OL) vs Sink

Current (I_OL

图 4. Typical (T_A=25°C) Output High Voltage (V_OL) vs Sink

Current (I_OL

)

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7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

•

f = 1 MHz

Z_O= 50 Ω

dv/dt ≤ 1 ns/V

Measurement Point

2 x V_CCO

Open

R_L

Output Pin

Under Test

GND

(1)

C_L

R_L

(1) C_Lincludes probe and jig capacitance.

图 5. Load Circuit

表 1. Load Circuit Conditions

Parameter

V_CCO

R_L

C_L

S₁

V_TP

N/A

Δt/Δv Input transition rise or fall rate

0.65 V – 3.6 V

1.1 V – 3.6 V

1 MΩ

2 kΩ

15 pF

Open

t_pdPropagation (delay) time

0.65 V – 0.95

20 kΩ

15 pF

Open

N/A

3 V – 3.6 V

1.65 V – 2.7 V

1.1 V – 1.6 V

2 kΩ

15 pF

2 × V_CCO

0.3 V

0.15 V

0.1 V

t_en, t_disEnable time, disable time

0.65 V – 0.95

20 kΩ

15 pF

2 × V_CCO

0.1 V

3 V – 3.6 V

1.65 V – 2.7 V

1.1 V – 1.6 V

2 kΩ

15 pF

GND

0.3 V

0.15 V

0.1 V

t_en, t_disEnable time, disable time

0.65 V – 0.95

20 kΩ

15 pF

GND

0.1 V

(1)

V_CCI

(1)

V_CCI

Input A, B

100 kHz

V_CCI/ 2

Input A, B

500 ps/V œ 10 ns/V

0 V

V_OH

0 V

V_OH

(2)

t_pd

(2)

Output B, A

Ensure Monotonic

Rising and Falling Edge

(2)

Output B, A

V_CCI/ 2

V_OL

(2)

V_OL

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur with

specified R_L, C_L, and S₁

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur with

specified R_L, C_L, and S₁

图 7. Input Transition Rise or Fall Rate

图 6. Propagation Delay

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V_CCA

GND

V_CCA/ 2

t_dis

t_en

(3)

V_CCO

Output⁽¹⁾

Output⁽²⁾

V_CCO/ 2

V_OL+ V_TP

(4)

V_OL

(4)

V_OH

V_OH- V_TP

V_CCO/ 2

GND

(1) Output waveform on the condition that input is driven to a valid Logic Low.

(2) Output waveform on the condition that input is driven to a valid Logic High.

(3) V_CCOis the supply pin associated with the output port.

(4) V_OHand V_OLare typical output voltage levels with specified R_L, C_L, and S₁.

图 8. Enable Time and Disable Time

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8 Detailed Description

8.1 Overview

The SN74AXCH4T245 is a 4-bit, dual-supply noninverting bidirectional voltage level translation device with bus-

hold inputs. xAx pins and control pins (1DIR, 2DIR, 1OE, and 2OE) are reference to V_CCAlogic levels, and xBx

pins are referenced to V_CCBlogic levels. The A port is able to accept I/O voltages ranging from 0.65 V to 3.6 V,

while the B port can accept I/O voltages from 0.65 V to 3.6 V. A high on DIR allows data transmission from A to

B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both

xAx and xBx pins are in the high-impedance state. See Device Functional Modes for a summary of the operation

of the control logic.

8.2 Functional Block Diagram

One of Two Transceiver Pairs

V_CCA

V_CCB

xDIR

xOE

Bus-Hold

xB1

xB2

xA1

xA2

Bus-Hold

Note: Bus-hold circuits are only present for data inputs, not control inputs

8.3 Feature Description

8.3.1 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input

capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum

input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the

Electrical Characteristics, using Ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating

Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a

device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

8.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device

creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at

all times.

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Feature Description (接下页)

8.3.3 Partial Power Down (I_off

)

The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting

current backflow into the device. The maximum leakage into or out of any input or output pin on the device is

specified by I_offin the Electrical Characteristics.

8.3.4 V_CCIsolation

The inputs and outputs for this device enter a high-impedance state when either supply is <100mV.

8.3.5 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum

input voltage value specified in the Recommended Operating Conditions.

8.3.6 Glitch-free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the

output erroneously transitions to VCC when it should be held low). Glitches of this nature can be misinterpreted

by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device

configuration of the peripheral, or even a false data initialization by the peripheral. For more information

regarding the power up glitch performance of the AXC family of level translators, see the Glitch Free Power

Sequencing With AXC Level Translators application report

8.3.7 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as depicted in 图 9.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can

cause damage to the device. The input negative-voltage and output voltage ratings

may be exceeded if the input and output clamp-current ratings are observed.

V_CC

Device

Input

Output

Logic

GND

-I_IK

-I_OK

图 9. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.8 Fully Configurable Dual-Rail Design

Both the V_CCAand V_CCBpins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for

translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V and 3.3 V).

8.3.9 Supports High-Speed Translation

The SN74AXCH4T245 device can support high data-rate applications. The translated signal data rate can be up

to 380 Mbps when the signal is translated from 1.8 V to 3.3 V.

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Feature Description (接下页)

8.3.10 Bus-Hold Data Inputs

Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of

these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low

state. After data has been sent through a channel, the latch then maintains the previous state on the input if the

line is left floating. It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as

it may cause undefined inputs to occur which leads to excessive current consumption.

Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs

application report explains the problems associated with leaving CMOS inputs floating.

These latches remain active at all times, independent of all control signals such as direction control or output

enable.

The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.

Input

Logic

Output

Bus-Hold Latch

图 10. Simplified Schematic For Device With Bus-Hold Data Inputs

8.4 Device Functional Modes

表 2. Function Table

(Each 2-Bit Section)⁽¹⁾⁽²⁾

CONTROL INPUTS

Port Status

OPERATION

DIR

A PORT

Output (Enabled)

Input (Hi-Z)

B PORT

Input (Hi-Z)

B data to A bus

A data to B bus

Isolation

Output (Enabled)

Input (Hi-Z)

(1) Input circuits of the data I/Os are always active.

(2) Bus-hold circuits of the data I/Os are always active, independent of the state of the control inputs.

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74AXCH4T245 device can be used in level-translation applications for interfacing devices or systems

operating at different interface voltages with one another. The SN74AXCH4T245 device is ideal for use in

applications where a push-pull driver is connected to the data I/Os. The max data rate can be up to 380 Mbps

when device translates a signal from 1.8 V to 3.3 V.

One example application is shown in 图 11, where the SN74AXCH4T245 device is used to translate a low

voltage UART signal from an SoC to a higher voltage signal which properly drive the inputs of the bluetooth

module, and vice versa.

9.2 Typical Application

Pullup Resistors keep device disabled

during power up. OE inputs may also

be tied to GND to keep device enabled

0.7 V

3.3 V

0.1 µF

V_CCA

V_CCB

1DIR

2DIR

1OE

GPIO1

Bluetooth

Module

GPIO2

SN74AXCH4T245

SoC

2OE

1A1

1A2

2A1

2A2

1B1

CTS

RTS

1B2

2B1

2B2

RTS

CTS

GND

图 11. UART Interface Application

9.2.1 Design Requirements

For this design example, use the parameters listed in 表 3.

表 3. Design Parameters

DESIGN PARAMETERS

Input voltage range

EXAMPLE VALUES

0.65 V to 3.6 V

Output voltage range

0.65 V to 3.6 V

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9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

•

Input voltage range

–

Use the supply voltage of the device that is driving the SN74AXCH4T245 device to determine the input

voltage range. For a valid logic-high, the value must exceed the high-level input voltage (V_IH) of the input

port. For a valid logic low the value must be less than the low-level input voltage (V_IL) of the input port.

•

Output voltage range

–

Use the supply voltage of the device that the SN74AXCH4T245 device is driving to determine the output

voltage range.

9.2.3 Application Curve

图 12. Up Translation at 2.5 MHz (0.7 V to 3.3 V)

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10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing

without any supply sequencing requirements such as ramp order or ramp rate.

This device was designed with various power supply sequencing methods in mind to help prevent unintended

triggering of downstream devices. For more information regarding the power up glitch performance of the AXC

family of level translators, see the Glitch Free Power Sequencing With AXC Level Translators application report

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

•

Use bypass capacitors on the power supply pins and place them as close to the device as possible.

Use short trace lengths to avoid excessive loading.

Do not use pullup or pulldown resistors on data inputs for devices with bus-hold circuits.

11.2 Layout Example

Legend

Via to V_CCA

Via to V_CCB

Via to GND

Copper Traces

SN74AXCH4T245PW

0.1µF

V_CCA

1DIR

2DIR

1A1

V_CCB

1OE

2OE

1B1

1B2

2B1

2B2

GND

RX to Module

TX from SoC

RTS from SoC

RX to SoC

CTS to Module

TX from Module

RTS from Module

1A2

2A1

CTS to SoC

2A2

GND

SN74AXCH4T245

www.ti.com.cn

ZHCSJI7 –MARCH 2019

12 器件和文档支持

12.1 相关文档ꢀ

请参阅如下相关文档：

德州仪器 (TI)，《慢速或浮点 CMOS 输入的影响》应用报告

德州仪器 (TI)，《AXC 系列器件电源定序》应用报告

德州仪器 (TI)，《利用总线保持电路避免浮点输入系统注意事项》应用报告

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

SN74AXCH4T245

ZHCSJI7 –MARCH 2019

www.ti.com.cn

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN74AXCH4T245PWR

SN74AXCH4T245RSVR

ACTIVE

TSSOP

UQFN

2000 RoHS & Green

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

S4TH245

1U7R

RSV

NIPDAUAG

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74AXCH4T245PWR TSSOP

SN74AXCH4T245RSVR UQFN

2000

3000

330.0

178.0

12.4

13.5

6.9

2.1

5.6

2.9

1.6

8.0

4.0

12.0

RSV

0.75

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74AXCH4T245PWR

SN74AXCH4T245RSVR

TSSOP

UQFN

2000

3000

356.0

189.0

356.0

185.0

35.0

36.0

RSV

Pack Materials-Page 2

PACKAGE OUTLINE

RSV0016A

UQFN - 0.55 mm max height

ULTRA THIN QUAD FLATPACK - NO LEAD

1.85

1.75

PIN 1 INDEX AREA

2.65

2.55

0.55

0.45

SEATING PLANE

0.05 C

0.05

0.00

2X 1.2

SYMM

℄

(0.13) TYP

0.45

0.35

15X

SYMM

℄

2X 1.2

12X 0.4

0.25

16X

0.15

0.07

0.05

C A B

0.55

0.45

PIN 1 ID

(45° X 0.1)

4220314/C 02/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RSV0016A

UQFN - 0.55 mm max height

ULTRA THIN QUAD FLATPACK - NO LEAD

SYMM

℄

(0.7)

SEE SOLDER MASK

DETAIL

16X (0.2)

SYMM

℄

12X (0.4)

(2.4)

(R0.05) TYP

15X (0.6)

(1.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4220314/C 02/2020

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RSV0016A

UQFN - 0.55 mm max height

ULTRA THIN QUAD FLATPACK - NO LEAD

(0.7)

16X (0.2)

SYMM

℄

12X (0.4)

(2.4)

(R0.05) TYP

15X (0.6)

SYMM

℄

(1.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 25X

4220314/C 02/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

14X 0.65

5.1

4.9

4.55

NOTE 3

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74AXCH4T245PWR [TI]

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