SN74BCT2240DWE4 [TI]
BCT/FBT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20;
| 型号： | SN74BCT2240DWE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BCT/FBT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54BCT2240, SN74BCT2240
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS030E – SEPTEMBER 1988 – REVISED MARCH 2003
SN54BCT2240 . . . J OR W PACKAGE
SN74BCT2240 . . . DB, DW, N,OR NS PACKAGE
(TOP VIEW)
Operating Voltage Range of 4.5 V to 5.5 V
State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
Output Ports Have Equivalent 33-Ω Series
Resistors, So No External Resistors Are
Required
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
description/ordering information
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. Together with the SN74BCT2241
and the ’BCT2244 devices, these devices provide
the choice of selected combinations of inverting
and noninverting outputs, symmetrical active-low
output-enable (OE) inputs, and complementary
OE and OE inputs. These devices feature high
fan-out and improved fan-in.
SN54BCT2240 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
4
5
6
7
8
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
17
16
15
14
The ’BCT2240 devices are organized as two 4-bit
line drivers with separate output-enable (OE)
inputs. When OE is low, the device passes data
from the A inputs to the Y outputs. When OE is
high, the outputs are in the high-impedance state.
9 10 11 12 13
To ensure the high-impedance state during power
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
Theoutputs, whicharedesignedtosourceorsinkupto12mA, include33-Ω seriesresistorstoreduceovershoot
and undershoot.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
Tube
SN74BCT2240N
SN74BCT2240N
Tube
SN74BCT2240DW
SN74BCT2240DWR
SN74BCT2240NSR
SN74BCT2240DBR
SNJ54BCT2240J
SNJ54BCT2240W
SNJ54BCT2240FK
SOIC – DW
BCT2240
0°C to 70°C
Tape and reel
Tape and reel
Tape and reel
Tube
SOP – NS
SSOP – DB
CDIP – J
BCT2240
BA240
SNJ54BCT2240J
SNJ54BCT2240W
SNJ54BCT2240FK
–55°C to 125°C
CFP – W
Tube
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT2240, SN74BCT2240
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS030E – SEPTEMBER 1988 – REVISED MARCH 2003
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
A
OE
L
H
L
L
H
Z
L
H
X
logic diagram (positive logic)
1
2
4
1OE
1A1
1A2
18
16
1Y1
1Y2
6
8
14
12
1A3
1A4
1Y3
1Y4
19
2OE
9
7
11
13
2A1
2A2
2Y1
2Y2
15
17
5
3
2A3
2A4
2Y3
2Y4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT2240, SN74BCT2240
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS030E – SEPTEMBER 1988 – REVISED MARCH 2003
schematic of Y outputs
V
CC
Output
GND
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
CC
Input clamp current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
IK
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT2240, SN74BCT2240
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS030E – SEPTEMBER 1988 – REVISED MARCH 2003
recommended operating conditions (see Note 3)
SN54BCT2240
MIN NOM MAX
SN74BCT2240
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
–12
12
0.8
–18
–12
12
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
–55
125
0
70
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54BCT2240
SN74BCT2240
PARAMETER
TEST CONDITIONS
UNIT
V
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
= 4.5 V
I = –18 mA
I
–1.2
–1.2
IK
CC
I
I
I
I
= –1 mA
= –12 mA
= 1 mA
2.4
2
3.3
3.2
2.4
2
3.3
3.2
OH
OH
OL
OL
V
OH
CC
0.15
0.35
0.5
0.8
0.1
20
0.15
0.35
0.5
0.8
0.1
20
V
OL
V
CC
= 4.5 V
V
= 12 mA
I
I
I
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
I
mA
µA
I
V = 2.7 V
I
IH
V = 0.5 V
I
–1
–1
mA
µA
IL
V
O
V
O
V
O
= 2.7 V
= 0.5 V
= 0
50
50
OZH
OZL
–50
–225
32
–50
–225
32
µA
‡
–100
–100
mA
mA
mA
mA
OS
Outputs open
Outputs open
Outputs open
19
46
6
19
46
6
CCH
CCL
CCZ
76
76
8
8
†
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C =50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54BCT2240 SN74BCT2240
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
0.5
0.5
2.6
4.3
2
TYP
3.4
2.8
6.2
8.8
5.3
6.7
MAX
4.8
4
MIN
0.5
0.5
2.6
4.3
2
MAX
6.3
MIN
0.5
0.5
2.6
4.3
2
MAX
5.7
t
t
PLH
PHL
PZH
A
Y
Y
Y
ns
ns
ns
4.6
4.4
t
8.2
10.9
7.1
8.5
10.1
12.9
9.2
9.3
OE
OE
t
12.4
8.7
PZL
t
PHZ
t
2.2
2.2
12.2
2.2
10.6
PLZ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT2240, SN74BCT2240
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS030E – SEPTEMBER 1988 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
7 V (t
, t
, O.C.)
PZL PLZ
Open
(all others)
S1
From Output
Under Test
Test
Point
C
L
R1
R1
(see Note A)
From Output
Under Test
Test
Point
C
L
R2
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
R
= R1 = R2
L
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3 V
0 V
1.5 V
1.5 V
3 V
Timing Input
(see Note B)
1.5 V
t
w
0 V
3 V
0 V
3 V
0 V
t
h
Low-Level
Pulse
t
1.5 V
su
1.5 V
Data Input
(see Note B)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level enable)
3 V
1.5 V
1.5 V
Input
(see Note B)
1.5 V
1.5 V
0 V
PHL
t
t
PZL
t
t
PLZ
t
PLH
3.5 V
In-Phase
Output
(see Note D)
V
OH
1.5 V
Waveform 1
(see Notes C and D)
1.5 V
1.5 V
1.5 V
t
V
OL
V
OL
0.3 V
t
PHZ
PLH
t
PHL
PZH
V
OH
V
OH
Out-of-Phase
Output
(see Note D)
Waveform 2
(see Notes C and D)
1.5 V
1.5 V
0.3 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = t ≤ 2.5 ns, duty cycle = 50%.
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9093901M2A
5962-9093901MRA
5962-9093901MSA
SN74BCT2240DBLE
SN74BCT2240DBR
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
1
1
1
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Call TI
ACTIVE
W
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74BCT2240DBRE4
SN74BCT2240DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
SOIC
SOIC
PDIP
SO
DB
DW
DW
DW
DW
N
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74BCT2240DWE4
SN74BCT2240DWR
SN74BCT2240DWRE4
SN74BCT2240N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74BCT2240NSR
SN74BCT2240NSRE4
NS
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54BCT2240FK
SNJ54BCT2240J
SNJ54BCT2240W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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