SN74BCT2423AFN [TI]
16-Bit Latched Multiplexer/Demultiplexer Bus Transceivers 68-PLCC 0 to 70;
| 型号： | SN74BCT2423AFN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Latched Multiplexer/Demultiplexer Bus Transceivers 68-PLCC 0 to 70 总线收发器 解复用器 |
| 文件： | 总14页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
Multiplexed Real-Time and Latched Data
BiCMOS Design Substantially Reduces
Standby Current
Byte Control for Byte-Write Applications
Useful in NuBus Interface Applications
Useful in Memory Interleave Applications
Dependable Texas Instruments Quality and
Reliability
SN74BCT2423A . . . FN PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
AENL
ABLEA
ABENL
GND
AB7
10
11
12
13
14
15
16
17
18
19
20
21
AENM
ALE
59
58
57
56
55
54
53
52
V
CC
V
CC
AB15
AB14
AB13
AB12
GND
AB6
AB5
AB4
GND
AB3
51 AB11
50 AB10
AB2
AB1
49
48
47
46
45
44
AB9
AB0 22
AB8
V
23
24
25
26
GND
CC
A/BSEL
BLE
ABENM
ABLEB
BENM
BENL
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NuBus is a trademark of Texas Instruments Incorporated.
Copyright 1990, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
SN74BCT2424A . . . FN PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
AENL
ABLEA
ABENL
GND
AENM
ALE
10
11
12
13
14
15
59
58
57
56
55
54
53
52
51
50
49
48
47
V
CC
V
CC
AB7
AB15
AB14
AB13
AB12
GND
AB11
AB10
AB9
AB6
AB5 16
17
18
19
20
21
22
23
24
25
26
AB4
GND
AB3
AB2
AB1
AB0
AB8
GND
V
CC
46 ABENM
45 ABLEB
44 BENM
A/BSEL
BLE
BENL
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
description
The’BCT2423Aand’BCT2424Aaregeneral-purpose16-bitbidirectionaltransceiverswithdatastoragelatches
and byte control circuitry arranged for use in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing
of address and data information in microprocessor- or bus-interface applications. These devices are also useful
in memory-interleaving applications. The ’BCT2423A and ’BCT2424A offer inverted and noninverted data
paths, respectively.
The ’BCT2423A and ’BCT2424A were designed using Texas Instruments BiCMOS process, which features
bipolar drive characteristics, but also greatly reduces the standby power of the device when disabled. This is
valuable when the device is not performing an address or data transfer.
Three 16-bit I/O ports, A15–A0, B15–B0, and AB15–AB0 are available for address and/or data transfer. The
AENM, AENL, BENM, BENL, ABENM, and ABENL inputs control the bus transceiver functions. These control
signals also allow byte-control of the most significant byte and least significant byte for each bus.
Address and/or data information can be stored using the internal storage latches. The ALE, BLE, ABLEA, and
ABLEB inputs are active low, and are used to control data storage. When the latch enable input is low, the latch
is transparent. When the latch enable input goes high, the data present at the inputs is latched, and remains
latched until the latch enable input is returned low.
Data on the ’A’ bus and ’B’ bus are multiplexed onto the ’AB’ bus via the A /BSEL control line. When A /BSEL
is low, A15–A0 is mapped to the AB15–AB0 outputs. When A /BSEL is high, B15–B0 is mapped to the
AB15–AB0 outputs.
The SN74BCT2423A and SN74BCT2424A are characterized for operation from 0°C to 70°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
†
logic symbol for the ’BCT2423A
Φ
LATCHED MUX/DMUX
’BCT2423A
59
10
60
9
11
45
12
46
22
ALE
AENL
AENM
A0
ALE
ABLEA
ABLEB
ABENL
ABENM
0
ABLEA
ABLEB
ABENL
ABENM
AB0
AENL
AENM
0
AL
2
7
8
A7
A8
66
19
17
ABL
3
4
AB3
AB4
AM
61
24
15
A15
14
48
ASEL
BSEL
0
A/BSEL
7
8
AB7
AB8
27
B0
BL
51
53
ABM
11
12
AB11
AB12
34
36
7
8
B7
B8
56
BM
13
AB15
43
25
26
44
15
B15
BLE
BLE
BENL
BENM
BENL
BENM
†
These logic symbols are in accordance with ANSI/IEEE Std 91-1984.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
†
logic symbol for the ’BCT2424A
Φ
LATCHED MUX/DMUX
’BCT2424A
59
11
45
12
46
22
ALE
AENL
AENM
A0
ALE
ABLEA
ABLEB
ABENL
ABENM
0
ABLEA
ABLEB
ABENL
ABENM
AB0
10
60
9
AENL
AENM
0
AL
2
7
8
A7
A8
66
19
17
ABL
3
4
AB3
AB4
AM
61
24
15
A15
14
48
ASEL
BSEL
0
A/BSEL
7
8
AB7
AB8
27
B0
BL
51
53
ABM
11
12
AB11
AB12
34
36
7
8
B7
B8
56
13
AB15
BM
43
25
26
44
15
B15
BLE
BLE
BENL
BENM
BENL
BENM
†
These logic symbols are in accordance with ANSI/IEEE Std 91-1984.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
logic diagram for ’BCT2423A (positive logic)
AENL
C1
D1
ABLEA
8
8
8
A7–A0
16X
16
8
A15–A8
AENM
16
C1
ALE
ABENL
16X
16
D1
C1
MUX
AB7–AB0
G1
A/BSEL
BLE
8
8
16
1
1
16X
AB15–AB8
ABENM
16
16
D1
BENL
C1
ABLEB
8
8
B7–B0
16X
16
D1
8
8
B15–B8
BENM
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
logic diagram for ’BCT2424A (positive logic)
AENL
C1
ABLEA
8
8
A7–A0
16X
16
D1
8
8
A15–A8
AENM
16
ALE
C1
ABENL
16X
16
D1
C1
MUX
AB7–AB0
G1
A/BSEL
BLE
8
8
16
1
1
16X
AB15–AB8
ABENM
16
16
D1
BENL
C1
ABLEB
8
8
B7–B0
16X
16
D1
8
8
B15–B8
BENM
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
Terminal Functions
TERMINAL PINS
DESCRIPTION
A bus. This 16-bit I/O port allows for transmission of data and/or address information to or from the AB bus.
Information transfer between the A bus and the AB bus is inverting for the ’BCT2423A and noninverting for the
’BCT2424A.
A15–A0
AB15–AB0
(’BCT2423A)
AB15–AB0
(’BCT2424A)
AB Bus. This 16-bit i/o port allows for multiplexed transmission of data and/or address information to or from the A
and B buses. Information transfer between the A, B, and AB buses is inverting for the ’BCT2423A and noninverting
for the ’BCT2424A.
AB Bus Output Enable, Least Significant Byte. This active-low input is used to enable the AB7–AB0 outputs. When
this input is high, the AB7–AB0 outputs are in the high-impedance state allowing for data input.
ABENL
ABENM
AB Bus Latch Enable, Most Significant Byte. This active-low input is used to enable the AB15–AB8 outputs. When
this input is high, the AB15–AB8 outputs are in the high-impedance state allowing for data input.
AB Bus Latch Enable to A Bus. This active-low input is used to control the latch that holds data received from the
AB bus (AB15–AB0) to be transferred to the A bus (A15–A0). When ABLEA is low, the latch is transparent. When
ABLEAtransitions to the high level, the data present at the AB15 –AB0 inputs is latched, and it remains latched while
ABLEA is high.
ABLEA
ABLEB
AB Bus Latch Enable to B Bus. This active-low input is used to control the latch that holds data received from the
AB bus (AB15–AB0) to be transferred to the B bus (B15–B0). When ABLEB is low, the latch is transparent. When
ABLEBtransitions to the high level, the data present at the AB15 –AB0 inputs is latched, and it remains latched while
ABLEB is high.
A/B Select Control. This input controls the A/B multiplexer. When the input is low, the A15–A0 is selected as input
to the AB15–AB0 outputs. When the input is high, B15–B0 is selected as input to the AB15–AB0 outputs.
A/BSEL
AENL
A Bus Output Enable, Least Significant Byte. This active-low input is used to enable the A7–A0 outputs. When this
input is high, the A7–A0 outputs are in the high-impedance state allowing for data input.
AENM
ALE
A Bus Output Enable, Most Significant Byte. This active-low input is used to enable the A15–A8 outputs. When this
input is high, the A15–A8 outputs are in the high-impedance state allowing for data input.
A Bus Latch Enable. This active-low input is used to control the latch that holds data received from the A bus
(A15 –A0). When ALE is low, that latch is transparent. When ALE transitions to the high level, the data present at
the A15–A0 inputs is latched and remains latched while ALE is high.
B15–B0
B Bus. This 16-bit I/O port allows for transmission of data and/or address information to or from the AB bus.
Information transfer between the B bus and the AB bus is inverting for the ’BCT2423A and noninverting for the
’BCT2424A.
BENL
BENM
BLE
B Bus Output Enable, Least Significant Byte. This active-low input is used to enable the B7–B0 outputs. When this
input is high, the B7–B0 outputs are in the high-impedance state allowing for data input.
B Bus Output Enable, Most Significant Byte. This active-low input is used to enable the B15–B8 outputs. When this
input is high, the B15–B8 outputs are in the high-impedance state allowing for data input.
B Bus Latch Enable. This active-low input is used to control the latch that holds data received from the B bus
(B15–B0). When BLE is low, that latch is transparent. When BLE transitions to the high level, that data present at
the B15–B0 inputs is latched and remains latched while BLE is high.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
Function Tables
DIRECTION A OR B TO AB
OUTPUTS
INPUTS
’BCT2423A
AB 15–8 AB 7–0
’BCT2424A
AB 15–8 AB 7–0
Ax
H
L
Bx
X
X
X
H
L
ALE
L
BLE
X
A/BSEL
ABENM
ABENL
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
H
L
H
L
H
H
L
L
X
X
X
X
X
X
X
X
X
H
X
X
L
AB
L
AB
H
0
0
L
H
H
H
X
X
X
X
X
L
H
L
X
X
X
X
X
X
H
X
AB
AB
0
0
X
Active
Active
Z
Active
Z
Active
Active
Z
Active
Z
X
X
X
X
Active
Z
Active
Z
X
X
Z
Z
DIRECTION AB TO A OR B
INPUTS
OUTPUTS
†
†
ABx
ABx
H
AENL
BENL
’BCT2423A
’BCT2424A
ABLEA
ABLEB
†
†
AENM
BENM
Ax
L
Bx
L
Ax
H
L
Bx
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
L
H
H
L
B
B
H
L
B
B
0
0
L
L
H
0
0
H
H
H
H
X
X
X
X
A
0
A
0
A
0
L
A
0
A
0
A
0
H
L
L
H
L
X
H
X
X
X
X
B
0
B
0
X
Active
Active
Z
Active
Z
Active
Active
Z
Active
Z
X
X
Active
Z
Active
Z
X
Z
Z
H = high level, L = low level, X = irrelevant, Z = high impedance.
A , B , AB , AB = no change since the controlling latch enable went high
0
0
0
0
†
The least significant bytes (A7-A0 and B7-B0) and the most significant bytes (A15-A8 and B15-B8) can be independently enabled and
disabled, as was illustrated for the AB and AB bytes in the upper function table.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
†
absolute maximum ratings over operating free-air temperature range(unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
CC
Input voltage (all inputs and I/O ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to 150° C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
PARAMETER
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
4.75
2
5
5.25
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.8
–15
–15
24
A , B outputs
x
x
I
I
t
High-level output current
Low-level output current
Pulse duration
mA
mA
ns
OH
OL
w
AB or AB outputs
x
x
A , B outputs
x
x
AB or AB outputs
48
x
x
ABLEA, ABLEB high or low
ALE, BLE high or low
Data before xLEx ↑
12.5
12.5
10
2
t
t
Setup time
ns
ns
°C
su
Hold time
Data after xLEx ↑
h
T
A
Operating free-air temperature
0
70
electrical characteristics over recommended operating free-air temperature range
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
= 4.75V,
I = –18 mA
–1.2
V
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
= 4.75V,
= 4.75V,
= 4.75V,
= 4.75V,
= 4.75V,
= 4.75V,
= 4.75V,
= 5.25V,
I
I
I
I
I
I
I
= –400
A
V
CC
– 1.5
OH
OH
OH
OL
OL
OL
OL
V
OH
= –3 mA
2.8
2
3.6
V
V
= –15 mA
= 12 mA
= 24 mA
= 24 mA
= 48 mA
0.25
0.35
0.25
0.35
0.4
0.5
0.4
0.5
100
A , B outputs
X
x
V
OL
A , B outputs
X
x
I
I
V = 5.5 V
I
A
A
I
20
–100
‡
V
CC
= 5.25V,
V = 2.7 V
I
IH
‡
I
I
V
V
V
V
= 5.25V,
= 5.25V,
= 5.25V,
V = 0.4 V
–200
–225
170
40
A
IL
CC
CC
CC
I
§
V
V
= 0
–60
mA
OS
0
Enabled
Disabled
= 0.5 V,
110
20
IL
I
mA
CC
= 3V,
Outputs open
IH
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
For I/O ports, the parameter I and I include the offstate output current.
IH
IL
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
‡
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
t
t
t
t
t
t
t
t
t
ABx, ABx
ABx, ABx
Ax
Ax
8
8
9
9
12
12
12
12
13
13
12
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
pd
pd
pd
pd
pd
pd
pd
pd
pd
Bx
ABx, ABx
ABx, ABx
ABx, ABx
ABx, ABx
Ax
Bx
ALE ↓
10
10
8
BLE ↓
ABLEA ↓
ABLEB ↓
A/BSEL
Bx
8
ABx, ABx
8
V
C
R
= 4.75 V to 5.25 V,
= 50 pF,
CC
L
1
AENM,
AENL
t
en
t
en
t
en
Ax
Bx
10
10
10
5
13
13
13
10
10
10
ns
ns
ns
ns
ns
ns
= 500 Ω, R = 500 Ω,
2
T
A
= MIN to MAX
BENM,
BENL
ABENM,
ABENL
ABx, ABx
Ax
AENM,
AENL
t
t
t
dis
dis
dis
BENM,
BENL
Bx
5
ABENM,
ABENL
ABx, ABx
5
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
See Parameter Measurement Information for load circuit and voltage waveforms.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
PARAMETER MEASUREMENT INFORMATION
7 V
SWITCH POSITION TABLE
R
= R = R
1
L
2
TEST
S1
S1
t
Open
Open
PLH
PHL
PZH
PZL
R1
t
t
t
t
t
From Output
Under Test
Test
Point
Open
Closed
Open
PHZ
PLZ
C
L
R2
(see Note A)
Closed
LOAD CIRCUIT
1.3 V
3.5 V
High-Level
3.5 V
0.3 V
1.3 V
1.3 V
Timing
Input
Pulse
1.3 V
0.3 V
t
w
t
h
t
su
3.5 V
0.3 V
3.5 V
0.3 V
Low-Level
Input
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output Control
(Low-level
3.5 V
0.3 V
1.3 V
1.3 V
1.3 V
1.3 V
Input
t
Enabling)
t
t
PZL
t
PHL
t
PLZ
PLH
V
V
OH
≈ 3.5 V
In-Phase
Output
1.3 V
1.3 V
1.3 V
Waveform 1
S1 Closed
(see Note B)
1.3 V
OL
V
OL
t
PLH
t
PHL
t
0.3 V
PHZ
V
V
PZH
OH
Out-of-Phase
Output
1.3 V
V
OH
Waveform 2
S1 Open
(see Note B)
OL
1.3 V
0.3 V
≈ 0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLED TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Wafeform 1 is for an output with internal conditions such that the output is low except when disabled by the current control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
APPLICATION INFORMATION
’ACT4503
ALE
ACR
AS
MA0–MA9
(see Note A)
ACW
R/W
M/IO
CS
RAS 0
CAS 0
RA0–RA9
BANK0
1M X 16BIT
A3–A12
DRAMs
A0–A9
A3–A22 ADDR BUS
CA0–CA9
A13–A22
RAS0
A2 (BANK SELECT
READY
RENO
RDY
RAS 1
A1 (BYTE
SELECT)
CAS 0
CAS 1
Lower Byte
Upper Strobe
A 2 (BYTE
SELECT)
W
D
Q
’BCT2424
AENM
A0–A15
AENL
ALE
BANK1
1M X 16BIT
DRAMs
B0–B15
A0–A9
ABLEA
ABENM
RAS1
CAS 0 Lower Byte
CAS 1
Upper Strobe
AB0–AB15
ABENL
D0–D15
DATA BUS
D
W
Q
ABLEB
ABSEL
BLE
BENM
BENL
NOTE A: The value of this delay element is dependent on the speed of the microprocessor.
Figure 2. Typical Memory Interleave Application
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PLCC
PLCC
Drawing
SN74BCT2423AFN
SN74BCT2424AFN
OBSOLETE
OBSOLETE
FN
68
68
TBD
TBD
Call TI
Call TI
Call TI
Call TI
FN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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