SN74BCT8373DW_技术文档

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

DW OR NT PACKAGE

(TOP VIEW)

• Member of the Texas Instruments SCOPE 

Family of Testability Products

• Octal Test-Integrated Circuit

LE

1Q

2Q

3Q

4Q

GND

5Q

6Q

OE

1D

2D

3D

4D

5D

V

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

• Functionally Equivalent to SN74F373 and

SN74BCT373 in the Normal-Function Mode

• Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

• Test Operation Synchronous to Test

CC

6D

7D

Access Port (TAP)

7Q

• Implements Optional Test Reset Signal by

Recognizing a Double-High-Level Voltage

(10 V) on TMS Pin

8Q 10

15 8D

TDO

TMS

TDI

TCK

11

12

14

13

• SCOPE  Instruction Set

− IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP

and HIGHZ

− Parallel-Signature Analysis at Inputs

− Pseudo-Random Pattern Generation

From Outputs

− Sample Inputs/Toggle Outputs

• Package Options Include Plastic

Small-Outline (DW) Packages and

Standard Plastic 300-mil DIPs (NT)

description

The SN74BCT8373 scan test device with octal D-type latches is a member of the Texas Instruments SCOPE

testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan

to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via

the 4-wire test access port (TAP) interface.

In the normal mode, this device is functionally equivalent to the SN74F373 and SN74BCT373 octal D-type

latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the

device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does

not affect the functional operation of the SCOPE octal latches.

In the test mode, the normal operation of the SCOPE octal latches is inhibited and the test circuitry is enabled

to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform

boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output

(TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing

functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation

(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN74BCT8373 is characterized for operation from 0°C to 70°C.

SCOPE is a trademark of Texas Instruments Incorporated.

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Copyright  1994, Texas Instruments Incorporated

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2−1

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

FUNCTION TABLE

(normal mode, each latch)

INPUTS

OUTPUT

Q

OE

L

LE

H

L

D

H

L

H

L

X

Q

0

H

X

Z

†

logic symbol

Φ

SCAN

SN74BCT8373

14

TDI

TMS

TCK

TDI

12

13

11

TMS

TDO

TCK-IN

TCK-OUT

EN

24

1

OE

LE

C1

1D

23

22

21

20

19

17

16

15

2

3

1D

2D

3D

4D

5D

6D

7D

8D

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

4

5

7

8

9

10

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2−2

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

functional block diagram

Boundary-Scan Register

V

CC

24

1

OE

LE

CC

C1

1D

V

CC

23

2

1D

1Q

One of Eight Channels

Bypass Register

Boundary-Control

Register

V

CC

V

CC

11

TDO

14

12

Instruction Register

TDI

TMS

TCK

CC

TAP

V

CC

Controller

13

2−3

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

Terminal Functions

TERMINAL

NAME

DESCRIPTION

Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if left

unconnected.

1D−8D

GND

LE

Ground

Normal-function latch-enable input. See function table for normal-mode logic. An internal pullup forces LE to a high level if

left unconnected.

Normal-function output-enable input. See function table for normal-mode logic. An internal pullup forces OE to a high level

if left unconnected.

OE

1Q−8Q

Normal-function data outputs. See function table for normal-mode logic.

Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to

TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces

TCK to a high level if left unconnected.

TCK

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through

the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data

through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active

and is not driven from an external source.

TDO

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP

controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test reset

TMS

signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (V

), at TMS.

IHH

V

CC

Supply voltage

2−4

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

test architecture

Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard

1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The

TAP controller monitors two signals from the test bus, namely TCK and TMS. The TAP controller extracts the

synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip

control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and

output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully

one-half of the TCK cycle.

The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan

architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated,

the device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register,

a 2-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

TMS = H

TMS = L

TMS = H

Run-Test/Idle

Select-DR-Scan

TMS = L

Select-IR-Scan

TMS = L

TMS = H

Capture-DR

TMS = L

Capture-IR

TMS = L

Shift-DR

Shift-IR

TMS = L

TMS = H

Exit1-IR

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = H

Pause-IR

TMS = H

Exit2-IR

TMS = L

Exit2-DR

TMS = H

Update-IR

Update-DR

TMS = H

TMS = L

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

2−5

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

state diagram description

The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.

The state diagram is illustrated in Figure 1 and is in accordance with IEEE Standard 1149.1-1990. The TAP

controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As illustrated, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow

in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for

consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and

one to access and control the instruction register. Only one register may be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset

and is disabled so that the normal logic function of the device is performed. The instruction register is reset to

an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data

registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more

than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left

unconnected or if a board defect causes it to be open circuited.

For the SN74BCT8373, the instruction register is reset to the binary value 11111111, which selects the BYPASS

instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test

operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.

Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle.

The test operations selected by the boundary-control register are performed while the TAP controller is in the

Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits

either of these states on the next TCK cycle. These states allow the selection of either data-register scan or

instruction-register scan.

Capture-DR

Upon entry to the Capture-DR state, the data register is placed in the scan path between TDI and TDO and,

on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. If the TAP controller

has not passed through the Test-Logic-Reset state since the last scan operation, TDO will enable to the level

present when it was last disabled. If the TAP controller has passed through the Test-Logic-Reset state since the

last scan operation, TDO will enable to a low level.

In the Capture-DR state, the selected data register may capture a data value as specified by the current

instruction. Such capture operations occur on the rising edge of TCK upon which the TAP controller exits the

Capture-DR state.

2−6

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

Shift-DR

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.

The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during

the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).

The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return

to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain

indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, then such update

occurs on the falling edge of TCK following entry to the Update-DR state, at which time TDO also goes from the

active state to the high-impedance state.

Capture-IR

In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs

on the rising edge of TCK upon which the TAP controller exits the Capture-IR state.

Upon entry to the Capture-IR state, the instruction register is placed in the scan path between TDI and TDO and,

on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. If the TAP controller

has not passed through the Test-Logic-Reset state since the last scan operation, TDO will enable to the level

present when it was last disabled. If the TAP controller has passed through the Test-Logic-Reset state since the

last scan operation, TDO will enable to a low level.

For the SN74BCT8373, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK

cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs

during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to

Shift-IR). The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to

return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely.

The Pause-IR state suspends and resumes instruction-register scan operations without loss of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK following entry to the Update-IR

state, at which time TDO also goes from the active state to the high-impedance state.

2−7

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

register overview

With the exception of the bypass register, any test register may be thought of as a serial-shift register with a

shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the

appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register

may be parallel loaded from a source specified by the current instruction. During the appropriate shift state

(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted

in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from

the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information

contained in the instruction includes the mode of operation (either normal mode, in which the device performs

its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation

to be performed, which of the three data registers is to be selected for inclusion in the scan path during

data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 2 lists the instructions supported by the SN74BCT8373. The even-parity feature specified for SCOPE

devices is not supported in this device. Bit 7 of the instruction opcode is a don’t-care bit. Any instructions that

are defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted

out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value

that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated

and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the

binary value 11111111, which selects the BYPASS instruction. The IR order of scan is illustrated in Figure 2.

Bit 7

(MSB)

Don’t

Care

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TDI

TDO

Figure 2. Instruction Register Order of Scan

2−8

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

data register description

boundary-scan register

The boundary-scan register (BSR) is 18 bits long. It contains one boundary-scan cell (BSC) for each

normal-function input pin and one BSC for each normal-function output pin. The BSR is used 1) to store test

data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output

terminals, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or

externally at the device input terminals.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The

contents of the BSR may change during Run-Test/Idle as determined by the current instruction. The contents

of the BSR are not changed in Test-Logic-Reset.

The BSR order of scan is from TDI through bits 17−0 to TDO. Table 1 shows the BSR bits and their associated

device pin signals.

Table 1. Boundary-Scan-Register Configuration

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

17

16

−

LE

OE

−

15

14

13

12

11

10

9

1D

2D

3D

4D

5D

6D

7D

8D

7

6

5

4

3

2

1

0

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

−

8

boundary-control register

The boundary-control register (BCR) is two bits long. The BCR is used in the context of the RUNT instruction

to implement additional test operations not included in the basic SCOPE instruction set. Such operations

include PRPG and PSA. Table 3 shows the test operations that are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is

reset to the binary value 10, which selects the PSA test operation. The BCR order of scan is illustrated in

Figure 3.

Bit 1

(MSB)

Bit 0

(LSB)

TDI

TDO

Figure 3. Boundary-Control Register Order of Scan

2−9

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,

thereby reducing the number of bits per test pattern that must be applied to complete a test operation.

During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is illustrated in

Figure 4.

TDI

TDO

Bit 0

Figure 4. Bypass Register Order of Scan

instruction-register opcode description

The instruction-register opcodes are shown in Table 2. The following descriptions detail the operation of each

instruction.

Table 2. Instruction Register Opcodes

†

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

SELECTED DATA

REGISTER

SCOPE OPCODE

DESCRIPTION

MODE

X0000000

X0000001

X0000010

X0000011

X0000100

X0000101

X0000110

X0000111

X0001000

X0001001

X0001010

X0001011

X0001100

X0001101

X0001110

X0001111

All others

EXTEST

Boundary scan

Bypass scan

Boundary scan

Bypass

Test

Normal

Test

‡

BYPASS

SAMPLE/PRELOAD

INTEST

Sample boundary

Boundary scan

Bypass

Boundary scan

‡

BYPASS

Bypass scan

Normal

Modified test

Test

‡

Bypass scan

Bypass

HIGHZ (TRIBYP)

CLAMP (SETBYP)

Control boundary to high impedance

Control boundary to 1/0

Bypass scan

Bypass

‡

BYPASS

RUNT

Bypass

Normal

Test

Boundary run test

Bypass

READBN

READBT

CELLTST

TOPHIP

Boundary read

Boundary scan

Bypass

Normal

Test

Boundary read

Boundary self test

Boundary toggle outputs

Boundary-control register scan

Bypass scan

Normal

Test

SCANCN

SCANCT

BYPASS

Boundary control

Bypass

Normal

Test

Normal

†

‡

Bit 7 is a don’t-care bit; X = don’t care.

The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the SN74BCT8373.

2−10

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

boundary scan

This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is

selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data

appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned

into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into

the output BSCs is applied to the device output terminals. The device operates in the test mode.

bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is

selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data

appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the

normal mode.

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in a modified test mode in which all device output terminals are placed in the high-impedance state,

the device input terminals remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input

BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device

output terminals. The device operates in the test mode.

boundary run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during

Run-Test/Idle. The four test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),

PRPG, PSA, and simultaneous PSA and PRPG (PSA/PRPG).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This

instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.

In this way, the contents of the shadow latches may be read out to verify the integrity of both shift-register and

shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. Data in the shift register elements of the selected output BSCs is toggled on each rising edge of

TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device output

terminals on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and

is applied to the inputs of the normal on-chip logic. Data appearing at the device input terminals is not captured

in the input BSCs. The device operates in the test mode.

2−11

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This

operation must be performed before a boundary-run test operation to specify which test operation is to be

executed.

boundary-control-register opcode description

The BCR opcodes are decoded from BCR bits 1−0 as shown in Table 3. The selected test operation is

performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail

the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 3. Boundary-Control-Register Opcodes

BINARY CODE

BIT 1 → BIT 0

MSB → LSB

DESCRIPTION

00

01

10

11

Sample inputs/toggle outputs (TOPSIP)

Pseudo-random pattern generation/16-bit mode (PRPG)

Parallel-signature analysis/16-bit mode (PSA)

Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)

It should be noted, in general, that while the control input BSCs (bits 17−16) are not included in the sample,

toggle, PSA, or PRPG algorithms, the output-enable BSC (bit 16 of the BSR) does control the drive state (active

or high impedance) of the device output terminals.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the device input terminals is captured in the shift-register elements of the input BSCs on each

rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs

of the normal on-chip logic. Data in the shift register elements of the output BSCs is toggled on each rising edge

of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK.

2−12

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the BSCs on each rising edge of TCK

and then updated in the shadow latches and applied to the device output terminals on each falling edge of TCK.

This data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip

logic. Figure 5 illustrates the 16-bit linear-feedback shift-register algorithm through which the patterns are

generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value

of all zeroes will not produce additional patterns.

1D

2D

3D

4D

5D

6D

7D

8D

=

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

Figure 5. 16-Bit PRPG Configuration

parallel-signature analysis (PSA)

Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register

elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input

BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs

remains constant and is applied to the device outputs. Figure 6 illustrates the 16-bit linear-feedback shift-register

algorithm through which the signature is generated. An initial seed value should be scanned into the BSR before

performing this operation.

1D

2D

3D

4D

5D

6D

7D

8D

=

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

Figure 6. 16-Bit PSA Configuration

2−13

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register

elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the

input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random

pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in

the shadow latches, and applied to the device output terminals on each falling edge of TCK. Figure 7 illustrates

the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. An

initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes

will not produce additional patterns.

1D

2D

3D

4D

5D

6D

7D

8D

=

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

Figure 7. 8-Bit PSA/PRPG Configuration

2−14

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

timing description

All test operations of the SN74BCT8373 are synchronous to TCK. Data on the TDI, TMS, and normal-function

inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output terminals

on the falling edge of TCK. The TAP controller is advanced through its states (as illustrated in Figure 1) by

changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK.

A simple timing example is illustrated in Figure 8. In this example, the TAP controller begins in the

Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan

and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and TDO

is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 4 explains

the operation of the test circuitry during each TCK cycle.

Table 4. Explanation of Timing Example

TCK

CYCLE(S)

TAP STATE

AFTER TCK

DESCRIPTION

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward

the desired state.

1

Test-Logic-Reset

2

3

4

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

TDO becomes active on the falling edge of TCK. The IR captures the 8-bit binary value 10000001 on the rising

edge of TCK as the TAP controller exits the Capture-IR state.

5

6

Capture-IR

Shift-IR

TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as

the TAP controller advances to the next state.

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value

11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned

out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK

cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

7−13

Shift-IR

14

15

16

17

Exit1-IR

Update-IR

The IR is updated with the new instruction (BYPASS) and TDO becomes inactive (goes to the high-impedance

state) on the falling edge of TCK.

Select-DR-Scan

Capture-DR

TDO becomes active on the falling edge of TCK. The bypass register captures a logic 0 value on the rising

edge of TCK as the TAP controller exits the Capture-DR state.

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on

the rising edge of TCK as the TAP controller advances to the next state.

18

Shift-DR

19−20

21

Shift-DR

Exit1-DR

The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

In general, the selected data register is updated with the new data and TDO becomes inactive (goes to the

high-impedance state) on the falling edge of TCK.

22

Update-DR

23

24

25

Select-DR-Scan

Select-IR-Scan

Test-Logic-Reset Test operation completed

2−15

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TCK

TMS

TDI

TDO

TAP

Controller

State

3-State (TDO) or Don’t Care (TDI)

Figure 8. Timing Example

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage range, V : except TMS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

TMS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 12 V

Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V

Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

CC

Input clamp current, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA

IK

Current into any output in the low state: TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA

Any Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input voltage rating may be exceeded if the input clamp-current rating is observed.

recommended operating conditions

MIN NOM

MAX

UNIT

V

Supply voltage

4.5

2

5

5.5

CC

High-level input voltage

Double-high-level input voltage

Low-level input voltage

Input clamp current

V

IH

TMS

10

12

0.8

−18

−3

V

IHH

IL

V

I

IK

mA

TDO

I

High-level output current

mA

OH

OL

Any Q

TDO

−15

24

I

Low-level output current

mA

Any Q

64

T

A

Operating free-air temperature

0

70

°C

2−16

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

TEST CONDITIONS

I = −18 mA

MIN TYP

MAX

UNIT

V

IK

V

= 4.5 V,

−1.2

V

CC

I

= 4.75 V,

I

= −3 mA

= −15 mA

= −1 mA

= −3 mA

= 64 mA

= 24 mA

2.7

2.4

2

3.4

CC

OH

OL

Any Q

V

= 4.5 V

CC

3.1

V

OH

V

= 4.75 V,

2.7

2.5

2.4

3.4

CC

3.4

TDO

V

= 4.5 V

CC

3.3

Any Q

TDO

0.42

0.35

0.55

0.5

V

OL

V

I

V

= 5.5 V,

V = 5.5 V

0.1

mA

µA

I

CC

I

V = 2.7 V

I

−1

−35 −100

1

IH

TMS

V = 10 V

I

mA

µA

IHH

IL

V = 0.5 V

I

−70 −200

50

Any Q

TDO

I

V

CC

= 5.5 V,

V

O

= 2.7 V

µA

OZH

OZL

−1

−35 −100

−50

Any Q

TDO

I

V

= 5.5 V,

V

= 0.5 V

= 0

µA

CC

O

−70 −200

−225

‡

−100

mA

OS

CC

O

Outputs high

Outputs low

3.5

35

1.5

10

14

7

52

I

V

= 5.5 V,

Outputs open

mA

CC

Outputs disabled

3.5

C

V

= 5 V,

V = 2.5 V or 0.5 V

I

pF

i

CC

V

O

= 2.5 V or 0.5 V

o

CC

†

‡

All typical values are at V

= 5 V, T = 25°C.

A

CC

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

2−17

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SCBS471 − JUNE 1990 − REVISED JUNE 1994

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 9)

V

T

= 5 V,

= 25°C

CC

A

MIN

MAX

UNIT

MIN

5

MAX

t

w

t

su

t

h

Pulse duration

Setup time

Hold time

LE high

5

3

2

ns

Data before LE↓

Data after LE↓

3

2

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 9)

V

T

= 5 V,

= 25°C

CC

A

MIN

MAX

UNIT

MIN

0

MAX

f

t

Clock frequency

Pulse duration

TCK

20

0

25

50

6

20

MHz

ns

clock

TCK high or low

TMS double high

Any D before TCK↑

LE or OE before TCK↑

TDI before TCK↑

TMS before TCK↑

Any D after TCK↑

LE or OE after TCK↑

TDI after TCK↑

25

50

6

w

6

t

su

Setup time

ns

6

15

4.5

0

15

4.5

0

t

Hold time

ns

h

TMS after TCK↑

Power up to TCK↑

Delay time

100

d

2−18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢀꢅ ꢉꢁꢊꢆ ꢋꢀꢆ ꢊꢌ ꢋ ꢍꢎ ꢅ

ꢈ

ꢂ

ꢈ

ꢋ

ꢀ

ꢊ

ꢏ

ꢎ

ꢆ

ꢐ

ꢊ

ꢑꢅ

ꢆ

ꢉ

ꢒꢊ

ꢌ

ꢓ

ꢆ

ꢔ

ꢕ

ꢋ

ꢊ

ꢒ

ꢉ

ꢆ

ꢅ

ꢐ

ꢋ

SCBS471 − JUNE 1990 − REVISED JUNE 1994

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 9)

V

T

= 5 V,

= 25°C

CC

A

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

MIN

MAX

UNIT

MIN

2

TYP

5.6

5.5

6.7

5.6

6.8

5.7

5.5

MAX

9

t

2

10

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

D

Q

ns

2

9

3

10.5

9

3

11.4

11.6

10.6

12

LE

OE

3

2.4

3

2.4

3

10.9

9.5

9

2.5

2.4

2.5

2.4

10

9.5

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 9)

V

T

= 5 V,

= 25°C

CC

A

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

MIN

MAX

UNIT

MIN

20

TYP

MAX

f

t

20

3.9

3.2

6.2

6.6

4.7

5.5

2.4

3.2

6.9

7.8

3.4

3.6

2.6

2.2

5

MHz

ns

max

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

PHZ

PLZ

3.9

3.2

6.2

6.6

4.7

5.5

2.4

3.2

6.9

7.8

3.4

3.6

2.6

2.2

5

10.9

10.8

8.5

15.7

15.3

12.3

12

19.8

19.5

15.4

15

TCK↓

TCK↑

TCK↓

TCK↑

TCK↓

TCK↑

Q

TDO

Q

ns

8.3

13.7

15

21

25

22

26

11.7

13.6

6.2

16.7

19.7

9

21.1

22.9

10.8

12.6

27

Q

TDO

Q

7.6

10.6

21.7

24.9

13.2

14.6

10.2

8.7

15.5

17.6

9

29

17.3

17.8

12.8

11.6

22.8

22

Q

10

7.1

TDO

Q

5.9

12.7

12.2

18.3

17.5

4.6

2−19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢂ ꢈ

ꢀꢅ ꢉ ꢁ ꢊꢆ ꢋꢀ ꢆ ꢊ ꢌꢋ ꢍ ꢎ ꢅꢋ

ꢏꢎ ꢆ ꢐ ꢊꢑ ꢅꢆꢉ ꢒꢊ ꢌꢓꢆ ꢔ ꢕꢋ ꢊ ꢒꢉꢆꢅ ꢐꢋ ꢀ

ꢊ

SCBS471 − JUNE 1990 − REVISED JUNE 1994

PARAMETER MEASUREMENT INFORMATION

7 V (t

, t

, O.C.)

PZL PLZ

Open

(all others)

S1

From Output

Under Test

Test

Point

C

L

R1

(see Note A)

From Output

Under Test

Test

Point

C

L

R2

(see Note A)

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

R

= R1 = R2

L

LOAD CIRCUIT FOR

3-STATE AND OPEN-COLLECTOR OUTPUTS

High-Level

Pulse

(see Note B)

3 V

0 V

1.5 V

3 V

Timing Input

(see Note B)

1.5 V

t

w

0 V

3 V

0 V

3 V

0 V

t

h

Low-Level

Pulse

t

1.5 V

su

1.5 V

Data Input

(see Note B)

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

3 V

0 V

Output

Control

(low-level enable)

3 V

1.5 V

Input

(see Note B)

1.5 V

0 V

PHL

t

PZL

t

PLZ

t

PLH

3.5 V

In-Phase

Output

(see Note D)

V

OH

1.5 V

Waveform 1

(see Notes C and D)

1.5 V

t

V

OL

V

OL

0.3 V

t

PHZ

PLH

t

PHL

PZH

V

OH

V

OH

Out-of-Phase

Output

(see Note D)

Waveform 2

(see Notes C and D)

1.5 V

0.3 V

0 V

V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (see Note D)

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C includes probe and jig capacitance.

L

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = t ≤ 2.5 ns, duty cycle = 50%.

r

f

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. The outputs are measured one at a time with one transition per measurement.

E. When measuring propagation delay times of 3-state outputs, switch S1 is open.

Figure 9. Load Circuits and Voltage Waveforms

2−20

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^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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型号：	SN74BCT8373DW
厂家：	TEXAS INSTRUMENTS
描述：	SCAN TEST DEVICE WITH OCTAL D-TYPE LATCHES
文件：	总21页 (文件大小：293K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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