SN74CBT16800C [TI]
具有预充电输出和 –2V 下冲保护的 5V、1:1 (SPST)、20 通道 FET 总线开关;型号: | SN74CBT16800C |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有预充电输出和 –2V 下冲保护的 5V、1:1 (SPST)、20 通道 FET 总线开关 开关 |
文件: | 总5页 (文件大小:71K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74CBT16800
20-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS
SCDS090 – MAY 1999
DGG OR DGV PACKAGE
(TOP VIEW)
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
B-Port Outputs Are Precharged by Bias
Voltage to Minimize Signal Distortion
During Live Insertion
BIASV
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
2A1
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1
48
47
46
45
44
43
42
41
40
39
38
37
36
2
3
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
4
5
6
7
description
8
9
The SN74CBT16800 provides 20 bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay. The device also precharges the B port to a
user-selectable bias voltage (BIASV) to minimize
live-insertion noise.
10
11
12
13
35 2B1
34 2B2
33 2B3
2A2 14
15
2A3 16
V
CC
The device is organized as dual 10-bit bus
switches with separate output-enable (OE)
inputs. It can be used as two 10-bit bus switches
or one 20-bit bus switch. When OE is low, the
associated 10-bit bus switch is on and port A is
connected to port B. When OE is high, the switch
is open, the high-impedance state exists between
the two ports, and port B is precharged to BIASV
through the equivalent of a 10-kΩ resistor.
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
To ensure the high-impedance state during power
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN74CBT16800 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each 10-bit bus switch)
INPUT
FUNCTION
OE
L
A port = B port
A port = Z
B port = BIASV
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT16800
20-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS
SCDS090 – MAY 1999
logic diagram (positive logic)
1
BIASV
1B1
2
46
1A1
12
36
1A10
1B10
48
1OE
13
35
25
2A1
2B1
24
2A10
2B10
47
2OE
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Bias voltage range, BIASV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT16800
20-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS
SCDS090 – MAY 1999
recommended operating conditions (see Note 3)
MIN
4
MAX
UNIT
V
V
CC
Supply voltage
5.5
BIASV Supply voltage
1.3
2
V
V
CC
V
V
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
V
IH
0.8
85
V
IL
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to TI application report
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
±5
UNIT
V
V
IK
V
V
V
V
V
= 4.5 V,
= 5.5 V,
= 4.5 V,
= 5.5 V,
= 3.6 V,
CC
CC
CC
CC
CC
I
I
I
I
V = 5.5 V or GND
I
µA
mA
µA
mA
pF
I
BIASV = 2.4 V,
V
O
= 0
0.25
O
I
O
= 0,
V = V
I
or GND
50
CC
CC
‡
∆I
CC
Control inputs
One input at 2.7 V,
Other inputs at V
or GND
2.5
CC
C
C
Control inputs V = 3 V or 0
I
i
V
O
= 3 V or 0,
OE = V
pF
io(OFF)
CC
V
= 4 V,
CC
V
I
= 2.4 V,
I = 15 mA
I
TYP at V
= 4 V
CC
§
r
on
I = 64 mA
I
Ω
V = 0
I
V
CC
= 4.5 V
I = 30 mA
I
V = 2.4 V,
I
I = 15 mA
I
†
‡
§
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 5 V
CC
± 0.5 V
V
= 4 V
TEST
CONDITIONS
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
MIN MAX
¶
t
t
t
t
t
A or B
OE
B or A
A or B
ns
ns
pd
BIASV = GND
BIASV = 3 V
BIASV = GND
BIASV = 3 V
PZH
PZL
PHZ
PLZ
OE
A or B
ns
¶
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT16800
20-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS
SCDS090 – MAY 1999
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
S1
S1
500 Ω
t
pd
/t
Open
7 V
From Output
Under Test
t
GND
PLZ PZL
t
/t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
3 V
0 V
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
V
V
+ 0.3 V
Input
1.5 V
1.5 V
OL
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
C includes probe and jig capacitance.
L
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 1999, Texas Instruments Incorporated
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