SN74CBT16811CDGGR [TI]
24-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS 5-V BUS SWITCH WITH-2-V UNDERSHOOT PROTECTION; 与- 2 -V冲保护的预充电输出的5 V BUS开关24位FET总线开关
| 型号： | SN74CBT16811CDGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS 5-V BUS SWITCH WITH-2-V UNDERSHOOT PROTECTION |
| 文件： | 总11页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢇꢇꢄ
ꢊ ꢃ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢒꢓꢎ ꢄꢑꢔꢓ ꢕꢎ ꢖ ꢗ ꢏꢆ ꢒ ꢏꢆꢀ
ꢘ ꢋꢙ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢚ ꢊ ꢋꢙ ꢏꢁꢖ ꢎꢓꢀꢑ ꢗꢗ ꢆ ꢒꢓ ꢗ ꢆꢎ ꢄꢆ ꢌꢗ ꢁ
SCDS118C − JANUARY 2003 − REVISED OCTOBER 2003
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
D
D
D
Member of the Texas Instruments
Widebus Family
Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
1
56
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BIASV
1A1
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B11
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B11
2B12
2
3
B-Port Outputs Are Precharged by Bias
Voltage (BIASV) to Minimize Signal
Distortion During Live Insertion and
Hot-Plugging
1A2
4
1A3
5
1A4
6
1A5
7
1A6
D
D
D
D
Supports PCI Hot Plug
8
GND
1A7
Bidirectional Data Flow, With Near-Zero
Propagation Delay
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1A8
1A9
1A10
1A11
1A12
2A1
Low ON-State Resistance (r
)
on
Characteristics (r = 3 Ω Typical)
on
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(C
= 5.5 pF Typical)
io(OFF)
D
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
2A2
V
CC
Low Power Consumption
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
(I
= 3 µA Max)
CC
D
V
Operating Range From 4 V to 5.5 V
CC
D
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D
D
D
D
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
I
Supports Partial-Power-Down Mode
off
2A10
2A11
2A12
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
D
Supports Both Digital and Analog
Applications: PCI Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
description/ordering information
The SN74CBT16811C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),
on
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT16811C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state. The device also precharges the B port to a user-selectable bias
voltage (BIASV) to minimize live-insertion noise.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇꢇ ꢄ
ꢊꢃ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅ ꢏꢀ ꢀ ꢐꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢒ ꢓꢎ ꢄꢑ ꢔꢓꢕ ꢎꢖ ꢗ ꢏꢆ ꢒꢏꢆ ꢀ
ꢘꢋ ꢙ ꢅ ꢏ ꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢚ ꢊ ꢋꢙ ꢏꢁ ꢖꢎ ꢓꢀ ꢑ ꢗꢗ ꢆ ꢒꢓ ꢗꢆ ꢎꢄꢆ ꢌ ꢗ ꢁ
SCDS118C − JANUARY 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
The SN74CBT16811C is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs.
It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit
bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B
ports. The B port is precharged to BIASV through the equivalent of a 10-kΩ resistor when OE is high, or if the
device is powered down (V
= 0 V).
CC
During insertion (or removal) of a card into (or from) an active bus, the card’s output voltage may be close to
GND. When the connector pins make contact, the card’s parasitic capacitance tries to force the bus signal to
GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch
with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers
on the active bus. This method will ensure that any glitch produced by insertion (or removal) of the card will not
cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74CBT16811CDL
SSOP − DL
CBT16811C
Tape and reel
Tube
SN74CBT16811CDLR
SN74CBT16811CDGG
SN74CBT16811CDGGR
SN74CBT16811CDGVR
−40°C to 85°C
TSSOP − DGG
TVSOP − DGV
CBT16811C
CY811C
Tape and reel
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 12-bit bus switch)
INPUT INPUT/OUTPUT
FUNCTION
OE
A
L
B
A port = B port
Disconnect
B port = BIASV
H
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢊ ꢃ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢒꢓ ꢎꢄꢑꢔꢓ ꢕꢎ ꢖ ꢗ ꢏꢆ ꢒꢏ ꢆꢀ
ꢘ ꢋꢙ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢚ ꢊ ꢋꢙ ꢏꢁꢖ ꢎꢓꢀꢑ ꢗꢗ ꢆ ꢒꢓ ꢗ ꢆꢎ ꢄꢆ ꢌꢗ ꢁ
SCDS118C − JANUARY 2003 − REVISED OCTOBER 2003
logic diagram (positive logic)
1
BIASV
2
54
1A1
1B1
SW
SW
14
42
1A12
1B12
56
1OE
15
41
2A1
2B1
SW
SW
28
29
2A12
2B12
55
2OE
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
†
EN
†
EN is the internal enable signal applied to the switch.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇꢇ ꢄ
ꢊꢃ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅ ꢏꢀ ꢀ ꢐꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢒ ꢓꢎ ꢄꢑ ꢔꢓꢕ ꢎꢖ ꢗ ꢏꢆ ꢒꢏꢆ ꢀ
ꢘꢋ ꢙ ꢅ ꢏ ꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢚ ꢊ ꢋꢙ ꢏꢁ ꢖꢎ ꢓꢀ ꢑ ꢗꢗ ꢆ ꢒꢓ ꢗꢆ ꢎꢄꢆ ꢌ ꢗ ꢁ
SCDS118C − JANUARY 2003 − REVISED OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Bias supply voltage range, BIASV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
IN
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I/O
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK IN
I/OK I/O
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
I/O
Continuous current through V
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
4
MAX
UNIT
V
V
CC
Supply voltage
5.5
BIASV Bias supply voltage
0
V
V
CC
5.5
V
V
V
High-level control input voltage
Low-level control input voltage
Data input/output voltage
2
V
IH
0
0.8
5.5
85
V
IL
0
V
I/O
T
A
Operating free-air temperature
−40
°C
NOTE 6: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004. BIASV is a supply voltage, not a control input.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢇꢇꢄ
ꢊ ꢃ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢒꢓ ꢎꢄꢑꢔꢓ ꢕꢎ ꢖ ꢗ ꢏꢆ ꢒꢏ ꢆꢀ
ꢘ ꢋꢙ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢚ ꢊ ꢋꢙ ꢏꢁꢖ ꢎꢓꢀꢑ ꢗꢗ ꢆ ꢒꢓ ꢗ ꢆꢎ ꢄꢆ ꢌꢗ ꢁ
SCDS118C − JANUARY 2003 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Control inputs
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
= 4.5 V,
= 5 V,
I = −18 mA
IN
−1.8
V
IK
CC
0 mA > I ≥ −50 mA,
I
Data inputs
Switch OFF
Switch OFF
−2
V
V
IKU
CC
V
= V
or GND,
IN
CC
I = −10 mA,
I
‡
V
CC
= BIASV = 5 V,
3
V
V
O(USP)
V
IN
= V
or GND,
CC
V
V
= 0 V,
BIASV = V ,
I = 0
O
V −0.1
x
V
x
V
B port
CC
x
O
I
IN
Control inputs
= 5.5 V,
V = V
IN CC
or GND
1
µA
CC
BIASV = 2.4 V,
Switch OFF,
V = V or GND
IN
I
B port
V
= 4.5 V,
0.25
mA
O
CC
V
V
= 0,
O
CC
Switch OFF,
V = V or GND
= 0 to 5.5 V,
O
§
I
I
I
V
V
V
= 5.5 V,
= 0,
10
10
3
µA
µA
µA
OZ
CC
CC
CC
CC
V = 0,
I
IN
V = 0
CC
V
= 0 to 5.5 V,
= 0,
= V or GND,
CC
off
O
I
I
V
I/O
= 5.5 V,
Switch ON or OFF
CC
IN
¶
∆I
Control inputs
Control inputs
A port
V
V
V
V
V
= 5.5 V,
One input at 3.4 V,
Other inputs at V
CC
or GND
2.5
mA
pF
pF
pF
CC
C
C
C
= 3 V or 0
= 3 V or 0,
= 3 V or 0,
4.5
5.5
in
IN
Switch OFF,
Switch ON,
V
V
= V
= V
or GND
or GND
io(OFF)
io(ON)
I/O
I/O
CC
IN
CC
15.5
IN
CC
= 4 V,
V = 2.4 V,
I
I
O
= −15 mA
8
12
TYP at V
CC
= 4 V
#
I
O
I
O
I
O
= 64 mA
= 30 mA
= −15 mA
3
3
5
6
6
Ω
r
on
V = 0
I
V
CC
= 4.5 V
V = 2.4 V,
I
10
V
†
‡
§
¶
#
and I refer to control inputs. V , V , I , and I refer to data pins.
IN
IN
I
O
I
O
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
A
CC
= A-port undershoot static protection.
V
O(USP)
For I/O ports, the parameter I
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at the specified voltage level, rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 5 V
CC
0.5 V
V
= 4 V
CC
TEST
CONDITIONS
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
||
pd
t
A or B
OE
B or A
A or B
0.24
6.5
6.5
6.5
6.5
0.15
ns
ns
t
t
t
t
1.5
1.5
1.5
1.5
6
6
6
6
BIASV = GND
BIASV = 3 V
BIASV = GND
BIASV = 3 V
PZH
PZL
PHZ
PLZ
A or B
ns
OE
||
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇꢇ ꢄ
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ꢘꢋ ꢙ ꢅ ꢏ ꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢚ ꢊ ꢋꢙ ꢏꢁ ꢖꢎ ꢓꢀ ꢑ ꢗꢗ ꢆ ꢒꢓ ꢗꢆ ꢎꢄꢆ ꢌ ꢗ ꢁ
SCDS118C − JANUARY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
7 V
Open
GND
Input Generator
50 Ω
S1
R
V
V
O
L
I
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
∆
C
R
V
CC
TEST
L
L
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
or GND
or GND
50 pF
50 pF
t
pd(s)
5 V 0.5 V
4 V
7 V
7 V
500 Ω
500 Ω
GND
GND
50 pF
50 pF
0.3 V
0.3 V
t
/t
PLZ PZL
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
50 pF
50 pF
0.3 V
0.3 V
t
/t
PHZ PZH
Output
Control
(V
3 V
0 V
1.5 V
1.5 V
)
IN
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
Output
Control
3 V
0 V
1.5 V
V
V
+ V
1.5 V
1.5 V
OL
∆
(V
IN
)
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− V
OH
∆
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
C includes probe and jig capacitance.
L
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
. The tpd propagation delay is the calculated RC time constant of the typical ON-state
pd(s)
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
74CBT16811CDGGRE4
74CBT16811CDGVRE4
SN74CBT16811CDGGR
SN74CBT16811CDGVR
SN74CBT16811CDLR
SN74CBT16811CDLRG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TSSOP
TVSOP
SSOP
DGV
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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