SN74CBT16861DGG [TI]
20-BIT FET BUS SWITCH; 20位FET总线开关
| 型号： | SN74CBT16861DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20-BIT FET BUS SWITCH |
| 文件： | 总5页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBT16861
20-BIT FET BUS SWITCH
SCDS068A – JULY 1998 – REVISED DECEMBER 1999
DGG OR DL PACKAGE
(TOP VIEW)
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
GND
NC
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
GND
V
CC
2
1OE
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1B10
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Shrink
Small-Outline (DL) Packages
3
4
5
6
description
7
8
The SN74CBT16861 provides 20 bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
CC
The device is organized as one dual 10-bit switch
with separate output-enable (OE) input. When OE
is low, the switch is on, and port A is connected to
port B. When OE is high, the switch is open, and
the high-impedance state exists between the two
ports.
2OE
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2B10
The SN74CBT16861 is characterized for
operation from –40°C to 85°C.
NC – No internal connection
FUNCTION TABLE
(each 10-bit bus switch)
INPUT
FUNCTION
OE
L
A port = B port
Disconnect
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT16861
20-BIT FET BUS SWITCH
SCDS068A – JULY 1998 – REVISED DECEMBER 1999
logic diagram (positive logic)
2
46
37
1A1
1B1
11
1A10
1B10
47
14
1OE
2A1
34
25
2B1
23
35
2A10
2OE
2B10
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK I/O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
4
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
V
0.8
85
V
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT16861
20-BIT FET BUS SWITCH
SCDS068A – JULY 1998 – REVISED DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
10
UNIT
V
IK
V
V
V
V
V
= 4.5 V,
= 0,
V
CC
CC
CC
CC
CC
I
V = 5.5 V
I
I
I
µA
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 5.5 V or GND
I
±1
I
I
O
= 0,
V = V
I
or GND
3
µA
mA
pF
CC
CC
‡
∆I
CC
Control inputs
One input at 3.4 V,
Other inputs at V
or GND
2.5
CC
C
C
Control inputs V = 3 V or 0
3
i
I
V
O
= 3 V or 0,
OE = V
5.5
pF
io(OFF)
CC
V
= 4 V,
CC
V = 2.4 V,
I
I = 15 mA
I
14
22
TYP at V
= 4 V,
CC
§
r
on
I = 64 mA
I
5
5
7
7
Ω
V = 0
I
V
CC
= 4.5 V
I = 30 mA
I
V = 2.4 V,
I
I = 15 mA
I
10
15
†
‡
§
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 5 V
CC
± 0.5 V
V
= 4 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
MIN
MAX
0.25
6.5
¶
t
t
t
A or B
OE
B or A
A or B
A or B
0.35
6.3
8
ns
ns
ns
pd
en
2.7
1.5
1.7
1.8
7.1
OE
dis
¶
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT16861
20-BIT FET BUS SWITCH
SCDS068A – JULY 1998 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
S1
S1
500 Ω
t
Open
7 V
pd
/t
From Output
Under Test
GND
t
PLZ PZL
/t
t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
3 V
0 V
1.5 V
1.5 V
LOAD CIRCUIT
t
t
t
PZL
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
V
+ 0.3 V
1.5 V
1.5 V
OL
(see Note B)
V
OL
OH
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
V
V
OH
V
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1999, Texas Instruments Incorporated
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