SN74CBT3126D [TI]
QUADRUPLE FET BUS SWITCH; 四路FET总线开关
| 型号： | SN74CBT3126D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE FET BUS SWITCH |
| 文件： | 总4页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020E – MAY 1995 – REVISED MAY 1998
D, DGV, OR PW PACKAGE
(TOP VIEW)
Standard ’126-Type Pinout (D, DGV, and PW
Packages)
5-Ω Switch Connection Between Two Ports
1OE
1A
1B
2OE
2A
2B
V
CC
13 4OE
1
2
3
4
5
6
7
14
TTL-Compatible Input Levels
Latch-Up Performance Exceeds 250 mA Per
JESD 17
12 4A
11 4B
10 3OE
Package Options Include Plastic
9
8
3A
3B
Small-Outline (D), Shrink Small-Outline
(DBQ), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages
GND
DBQ PACKAGE
(TOP VIEW)
description
The SN74CBT3126 quadruple FET bus switch
features independent line switches. Each switch
is disabled when the associated output-enable
(OE) input is low.
V
4OE
NC
1OE
1A
1B
2OE
2A
1
2
3
4
5
6
7
8
16
15
CC
14 4A
13 4B
12 3OE
11 3A
The SN74CBT3126 is characterized for operation
from –40°C to 85°C.
10
9
3B
NC
2B
GND
FUNCTION TABLE
(each bus switch)
INPUT
FUNCTION
OE
NC – No internal connection
L
Disconnect
A = B
H
logic diagram (positive logic)
2
3
1A
1B
1
5
1OE
2A
6
8
2B
3B
4
9
2OE
3A
10
12
3OE
4A
11
4B
13
4OE
Pin numbers shown are for the D, DGV, and PW packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020E – MAY 1995 – REVISED MAY 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
K
I/O
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
JA
DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
4
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
V
0.8
85
V
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
±1
UNIT
V
V
V
V
V
V
= 4 V,
IK
CC
CC
CC
CC
I
I
I
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 5.5 V or GND
I
µA
µA
mA
pF
I
I
O
= 0,
V = V
I
or GND
3
CC
CC
§
∆I
CC
Control inputs
One input at 3.4 V,
Other inputs at V
or GND
2.5
CC
C
C
Control inputs V = 3 V or 0
3
4
i
I
V
O
= 3 V or 0,
OE = GND
pF
io(OFF)
V
= 4 V,
TYP at V
= 4 V,
V
= 2.4 V,
I = 15 mA
I
16
5
22
7
CC
CC
I
I = 64 mA
I
¶
r
V
V
= 0
Ω
on
I
V
CC
= 4.5 V
I = 30 mA
I
5
7
= 2.4 V,
I = 15 mA
I
10
15
I
‡
§
¶
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020E – MAY 1995 – REVISED MAY 1998
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 5 V
CC
± 0.5 V
V
= 4 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
MIN
MAX
0.25
5.1
†
A or B
OE
B or A
A or B
A or B
0.35
5.4
5
ns
ns
ns
t
t
t
pd
en
dis
1.6
1
OE
4.5
†
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
S1
Open
GND
500 Ω
t
Open
7 V
pd
/t
From Output
Under Test
t
PLZ PZL
t
/t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
3 V
0 V
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PZL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
V
OL
+ 0.3 V
1.5 V
1.5 V
(see Note B)
V
OL
t
PHZ
t
t
PZH
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
V
OH
– 0.3 V
0 V
1.5 V
Output
1.5 V
1.5 V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
PROPAGATION DELAY TIMES
C includes probe and jig capacitance.
L
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
andt
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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