SN74CBT3245CPWG4 [TI]
CBT/FST/QS/5C/B SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20;
| 型号： | SN74CBT3245CPWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CBT/FST/QS/5C/B SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总20页 (文件大小：893K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCDS131A − SEPTEMBER 2003 − REVISED OCTOBER 2003
D
D
D
D
Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
D
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Bidirectional Data Flow, With Near-Zero
Propagation Delay
D
D
D
I
Supports Partial-Power-Down Mode
off
Operation
Low ON-State Resistance (r
)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
on
Characteristics (r = 3 Ω Typical)
on
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
(C
= 5.5 pF Typical)
io(OFF)
− 1000-V Charged-Device Model (C101)
D
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
D
Supports Both Digital and Analog
Applications: USB Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
Low Power Consumption
(I
= 3 µA Max)
CC
D
V
Operating Range From 4 V to 5.5 V
CC
D
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
NC
A1
A2
A3
A4
A5
A6
A7
A8
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
20
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
OE
B1
B2
B3
B4
B5
B6
B7
GND
10
11
NC − No internal connection
NC − No internal connection
description/ordering information
The SN74CBT3245C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),
on
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT3245C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT3245C is organized as an 8-bit bus switch with a single output-enable (OE) input. When OE is
low, the bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between
ports. When OE is high, the bus switch is OFF, and the high-impedance state exists between the A and B ports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢉ ꢄ
ꢊꢋ ꢅꢌ ꢆ ꢍ ꢎꢆ ꢅ ꢏ ꢀ ꢀ ꢐꢌ ꢆ ꢄꢑ
ꢉꢋ ꢒ ꢅ ꢏ ꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢓ ꢈ ꢋꢒ ꢏꢁ ꢔꢎ ꢕꢀ ꢑ ꢖꢖ ꢆ ꢗꢕꢖ ꢆ ꢎꢄ ꢆꢌ ꢖ ꢁ
SCDS131A − SEPTEMBER 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − DW
Tape and reel
SN74CBT3245CRGYR
SN74CBT3245CDW
SN74CBT3245CDWR
SN74CBT3245CDB
SN74CBT3245CDBR
SN74CBT3245CDBQR
SN74CBT3245CPW
SN74CBT3245CPWR
SN74CBT3245CDGVR
CU245C
Tube
CBT3245C
Tape and reel
Tube
SSOP − DB
CU245C
−40°C to 85°C
Tape and reel
SSOP (QSOP) − DBQ Tape and reel
Tube
CBT3245C
TSSOP − PW
CU245C
CU245C
Tape and reel
TVSOP − DGV
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUT INPUT/OUTPUT
FUNCTION
OE
L
A
B
Z
A port = B port
Disconnect
H
logic diagram (positive logic)
2
18
11
A1
B1
B8
SW
SW
9
A8
19
OE
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS131A − SEPTEMBER 2003 − REVISED OCTOBER 2003
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
†
EN
†
EN is the internal enable signal applied to the switch.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 5): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
.
I
O
I/O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN
4
MAX
5.5
5.5
0.8
5.5
85
UNIT
V
V
V
V
V
Supply voltage
CC
High-level control input voltage
Low-level control input voltage
Data input/output voltage
Operating free-air temperature
2
V
IH
0
V
IL
0
V
I/O
T
A
−40
°C
NOTE 7: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢉ ꢄ
ꢊꢋ ꢅꢌ ꢆ ꢍ ꢎꢆ ꢅ ꢏ ꢀ ꢀ ꢐꢌ ꢆ ꢄꢑ
ꢉꢋ ꢒ ꢅ ꢏ ꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢓ ꢈ ꢋꢒ ꢏꢁ ꢔꢎ ꢕꢀ ꢑ ꢖꢖ ꢆ ꢗꢕꢖ ꢆ ꢎꢄ ꢆꢌ ꢖ ꢁ
SCDS131A − SEPTEMBER 2003 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Control inputs
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 4.5 V,
= 5 V,
I = −18 mA
IN
−1.8
V
IK
CC
CC
CC
CC
CC
CC
CC
0 mA > I ≥ −50 mA,
I
Data inputs
Switch OFF
Switch OFF,
−2
1
V
IKU
V
V
V
= V
or GND,
IN
IN
O
CC
I
I
I
I
Control inputs
= 5.5 V,
= 5.5 V,
= 0,
= V
or GND
µA
µA
µA
µA
IN
CC
= 0 to 5.5 V,
‡
10
10
3
OZ
off
V = 0,
V
= V or GND
CC
I
IN
V = 0
V
O
= 0 to 5.5 V,
= 0,
= V or GND,
CC
I
I
V
I/O
IN
= 5.5 V,
Switch ON or OFF
CC
§
∆I
Control inputs
Control inputs
V
V
V
V
V
= 5.5 V,
One input at 3.4 V,
Other inputs at V
CC
or GND
2.5
mA
pF
pF
pF
CC
C
C
C
= 3 V or 0
= 3 V or 0,
= 3 V or 0,
4
in
IN
Switch OFF,
Switch ON,
V
V
= V
= V
or GND
or GND
5.5
14
io(OFF)
io(ON)
I/O
I/O
CC
IN
CC
IN
CC
= 4 V,
V = 2.4 V,
I
O
= −15 mA
8
12
I
TYP at V
CC
= 4 V
¶
I
O
I
O
I
O
= 64 mA
= 30 mA
= −15 mA
3
3
5
6
6
Ω
r
on
V = 0
I
V
CC
= 4.5 V
V = 2.4 V,
I
10
V
†
‡
§
¶
and I refer to control inputs. V , V , I , and I refer to data pins.
IN
IN
I
O
I
O
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
CC
A
For I/O ports, the parameter I
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at the specified voltage level, rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
V
= 5 V
CC
0.5 V
V
= 4 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
#
t
t
t
A or B
OE
B or A
A or B
A or B
0.24
5.1
0.15
4.7
ns
ns
ns
pd
en
1.5
1.5
4.9
5.3
OE
dis
#
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS131A − SEPTEMBER 2003 − REVISED OCTOBER 2003
undershoot characteristics (see Figures 1 and 2)
†
PARAMETER
TEST CONDITIONS
Switch OFF,
= 5 V (unless otherwise noted), T = 25°C.
MIN
TYP
MAX
UNIT
V
V
CC
= 5.5 V,
V
IN
= V
CC
or GND
2
V
−0.3
V
OUTU
OH
†
All typical values are at V
CC
A
V
CC
11 V
100 kΩ
5.5 V
Input
(Open
Socket)
Input
Generator
90 %
10 %
90 %
10 %
50 Ω
2 ns 2 ns
20 ns
DUT
Ax
Bx
−2 V
100 kΩ
10 pF
V
S
Output
V
OH
V
OH
(V
OUTU
)
− 0.3
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage (V ) and Output
I
Voltage (V
) Waveforms
OUTU
(Switch OFF)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢉ ꢄ
ꢊꢋ ꢅꢌ ꢆ ꢍ ꢎꢆ ꢅ ꢏ ꢀ ꢀ ꢐꢌ ꢆ ꢄꢑ
ꢉꢋ ꢒ ꢅ ꢏ ꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢓ ꢈ ꢋꢒ ꢏꢁ ꢔꢎ ꢕꢀ ꢑ ꢖꢖ ꢆ ꢗꢕꢖ ꢆ ꢎꢄ ꢆꢌ ꢖ ꢁ
SCDS131A − SEPTEMBER 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
7 V
Open
GND
Input Generator
50 Ω
S1
R
V
V
O
L
I
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
∆
C
R
V
CC
TEST
L
L
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
or GND
or GND
50 pF
50 pF
t
pd(s)
5 V 0.5 V
4 V
7 V
7 V
500 Ω
500 Ω
GND
GND
50 pF
50 pF
0.3 V
0.3 V
t
/t
PLZ PZL
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
50 pF
50 pF
0.3 V
0.3 V
t
/t
PHZ PZH
Output
Control
(V
3 V
0 V
1.5 V
1.5 V
)
IN
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
Output
Control
3 V
0 V
1.5 V
V
V
+ V
1.5 V
1.5 V
OL
∆
(V
IN
)
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− V
OH
∆
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
C includes probe and jig capacitance.
L
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
. The tpd propagation delay is the calculated RC time constant of the typical ON-state
pd(s)
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2009
PACKAGING INFORMATION
Orderable Device
SN74CBT3245CDBQR
SN74CBT3245CDBQRE4
SN74CBT3245CDBQRG4
SN74CBT3245CDBR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
DBQ
DBQ
DB
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP
SSOP
SSOP
TVSOP
TVSOP
TVSOP
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT3245CDBRE4
SN74CBT3245CDBRG4
SN74CBT3245CDGVR
SN74CBT3245CDGVRE4
SN74CBT3245CDGVRG4
SN74CBT3245CDW
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGV
DGV
DGV
DW
DW
DW
DW
DW
DW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT3245CDWE4
SN74CBT3245CDWG4
SN74CBT3245CDWR
SN74CBT3245CDWRE4
SN74CBT3245CDWRG4
SN74CBT3245CPW
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
VQFN
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT3245CPWE4
SN74CBT3245CPWG4
SN74CBT3245CPWR
SN74CBT3245CPWRE4
SN74CBT3245CPWRG4
SN74CBT3245CRGYR
SN74CBT3245CRGYRG4
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
RGY
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2009
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Dec-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74CBT3245CDBQR
SN74CBT3245CDBR
SSOP/
QSOP
DBQ
20
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SSOP
DB
DGV
DW
20
20
20
20
20
2000
2000
2000
2000
3000
330.0
330.0
330.0
330.0
180.0
16.4
12.4
24.4
16.4
12.4
8.2
7.0
7.5
5.6
2.5
1.6
2.7
1.6
1.6
12.0
8.0
16.0
12.0
24.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
SN74CBT3245CDGVR TVSOP
SN74CBT3245CDWR
SN74CBT3245CPWR
SN74CBT3245CRGYR
SOIC
TSSOP
VQFN
10.8
6.95
3.8
13.0
7.1
12.0
8.0
PW
RGY
4.8
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Dec-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74CBT3245CDBQR
SN74CBT3245CDBR
SN74CBT3245CDGVR
SN74CBT3245CDWR
SN74CBT3245CPWR
SN74CBT3245CRGYR
SSOP/QSOP
SSOP
DBQ
DB
20
20
20
20
20
20
2500
2000
2000
2000
2000
3000
346.0
346.0
346.0
346.0
346.0
190.5
346.0
346.0
346.0
346.0
346.0
212.7
33.0
33.0
29.0
41.0
33.0
31.8
TVSOP
SOIC
DGV
DW
TSSOP
VQFN
PW
RGY
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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