SN74CBT3245DBLE [TI]
Octal FET Bus Switch 20-SSOP -40 to 85;型号: | SN74CBT3245DBLE |
厂家: | TEXAS INSTRUMENTS |
描述: | Octal FET Bus Switch 20-SSOP -40 to 85 开关 |
文件: | 总4页 (文件大小:57K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74CBT3245
OCTAL BUS SWITCH
SCDS002C – NOVEMBER 1992 – REVISED MAY 1995
DB, DW, OR PW PACKAGE
(TOP VIEW)
Functionally Equivalent to QS3245
Standard ’245-Type Pinout
5-Ω Switch Connection Between Two Ports
TTL-Compatible Control Input Levels
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
NC
A1
A2
A3
A4
A5
A6
A7
A8
CC
OE
B1
B2
B3
B4
B5
Package Options Include Shrink
Small-Outline (DB), Plastic Small-Outline
(DW), and Thin Shrink Small-Outline (PW)
Packages
description
13 B6
12 B7
11 B8
The SN74CBT3245 provides eight bits of
high-speed TTL-compatible bus switching in a
standard ’245 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
GND
The device is organized as one 8-bit switch. When output enable (OE) is low, the switch is on and port A is
connected to port B. When OE is high, the switch is open and a high-impedance state exists between the two
ports.
The SN74CBT3245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS/
INPUT
OE
OUTPUTS
A,B
L
A = B
Z
H
logic diagram
A1
A8
B1
B8
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3245
OCTAL BUS SWITCH
SCDS002C – NOVEMBER 1992 – REVISED MAY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK I/O
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.6 W
A
DW package . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
recommended operating conditions
MIN
4
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
V
0.8
85
V
T
A
–40
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
±5
UNIT
V
V
V
V
V
V
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
IK
CC
CC
CC
CC
I
I
I
V = 5.5 V or GND
I
µA
µA
mA
pF
I
I
= 0,
V = V
I
or GND
50
CC
O
CC
§
∆I
CC
Control pins
Control pins
One input at 3.4 V,
Other inputs at V
or GND
3.5
CC
C
C
V = 3 V or 0
I
3
6
i
V
O
= 3 V or 0,
OE = V
pF
io(OFF)
CC
= 2.4 V,
V
CC
= 4 V,
V
I
I = 15 mA
I
V = 0,
I = 64 mA
5
5
7
7
I
I
¶
r
Ω
on
V
CC
= 4.5 V
V = 0,
I
I = 30 mA
I
V = 2.4 V,
I
I = 15 mA
I
10
15
‡
§
¶
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
or GND.
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3245
OCTAL BUS SWITCH
SCDS002C – NOVEMBER 1992 – REVISED MAY 1995
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
†
t
t
t
A or B
OE
B or A
A or B
A or B
0.25
ns
ns
ns
pd
en
OE
dis
†
This parameter is characterized but not tested. This propagation delay is based on the RC time constant of the typical on-state resistance of the
switch and a load capacitance of 50 pF.
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
S1
S1
t
Open
7 V
pd
/t
500 Ω
From Output
Under Test
t
PLZ PZL
/t
GND
t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PZL
t
PLZ
3.5 V
Output
Waveform 1
S1 at 7 V
3 V
0 V
1.5 V
Input
V
+ 0.3 V
– 0.3 V
1.5 V
1.5 V
OL
V
OL
OH
(see Note B)
t
PHZ
t
PLH
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
V
V
OH
V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 Ω, t
D. The outputs are measured one at a time with one transition per measurement.
2.5 ns, t
f
2.5 ns.
O
r
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
dis
are the same as t
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1999, Texas Instruments Incorporated
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