SN74CBT3253CDRE4 [TI]
具有 –2V 下冲保护的 5V、4:1、2 通道 FET 总线开关 | D | 16 | -40 to 85;型号: | SN74CBT3253CDRE4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 –2V 下冲保护的 5V、4:1、2 通道 FET 总线开关 | D | 16 | -40 to 85 开关 光电二极管 逻辑集成电路 复用器 解复用器 |
文件: | 总14页 (文件大小:398K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢊꢋꢌ ꢍ ꢎ ꢏꢐ ꢑꢏ ꢃ ꢑ ꢒꢆ ꢓ ꢋꢍꢆ ꢔꢕ ꢍꢒ ꢖꢒꢗꢘ ꢊꢒꢓ ꢋꢍꢆꢔ ꢕ ꢍꢒ ꢖꢒ
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SCDS123A − JULY 2003 − REVISED OCTOBER 2003
D, DB, DBQ, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
SN74CBT3253C Functionally Identical to
Industry-Standard ’3253 Function
Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
2OE
S0
2B4
2B3
2B2
2B1
2A
1OE
S1
CC
Bidirectional Data Flow, With Near-Zero
Propagation Delay
1B4
1B3
1B2
1B1
1A
Low ON-State Resistance (r
)
on
Characteristics (r = 3 Ω Typical)
on
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
GND
(C
= 5.5 pF Typical)
io(OFF)
D
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
RGY PACKAGE
(TOP VIEW)
Low Power Consumption
(I
= 3 µA Max)
CC
D
V
Operating Range From 4 V to 5.5 V
CC
1
16
D
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
15
14
13
12
11
10
S1
1B4
1B3
1B2
1B1
1A
2
3
4
5
6
7
2OE
S0
2B4
2B3
2B2
2B1
D
D
D
D
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
I
Supports Partial-Power-Down Mode
off
Operation
8
9
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
2
D
D
Supports I C Bus Expansion
Supports Both Digital and Analog
Applications: USB Interface, Bus Isolation,
Low-Distortion Signal Gating
description/ordering information
The SN74CBT3253C is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state
resistance (r ), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and
on
B ports of the SN74CBT3253C provides protection for undershoot up to −2 V by sensing an undershoot event
and ensuring that the switch remains in the proper OFF state.
The SN74CBT3253C is organized as two 1-of-4 multiplexer/demultiplexers with separate output-enable
(1OE, 2OE) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When
OE is low, the associated multiplexer/demultiplexer is enabled, and the A port is connected to the B port, allowing
bidirectional data flow between ports. When OE is high, the associated multiplexer/demultiplexer is disabled,
and a high-impedance state exists between the A and B ports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇ ꢄ
ꢊ ꢋꢌꢍ ꢎ ꢏꢐꢑ ꢏꢃ ꢑ ꢒ ꢆ ꢓꢋ ꢍꢆꢔ ꢕ ꢍ ꢒꢖ ꢒꢗ ꢘ ꢊꢒ ꢓꢋ ꢍꢆ ꢔꢕ ꢍꢒ ꢖꢒꢗ
ꢉꢏ ꢙ ꢅ ꢋ ꢀ ꢀꢚ ꢔ ꢆ ꢄꢛ ꢚ ꢔ ꢆꢛ ꢜ ꢈ ꢏꢙ ꢋꢁ ꢊꢒ ꢗꢀ ꢛꢐ ꢐ ꢆ ꢕꢗ ꢐꢆ ꢒꢄꢆ ꢔ ꢐ ꢁ
SCDS123A − JULY 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − D
Tape and reel
SN74CBT3253CRGYR
SN74CBT3253CD
CU253C
Tube
CBT3253C
Tape and reel
Tube
SN74CBT3253CDR
SN74CBT3253CDB
SN74CBT3253CDBR
SN74CBT3253CDBQR
SN74CBT3253CPW
−40°C to 85°C SSOP − DB
CU253C
Tape and reel
SSOP (QSOP) − DBQ Tape and reel
CBT3253C
Tube
TSSOP − PW
CU253C
Tape and reel
SN74CBT3253CPWR
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
INPUT/OUTPUT
A
FUNCTION
OE
L
S1
L
S0
L
B1
B2
B3
B4
Z
A port = B1 port
A port = B2 port
A port = B3 port
A port = B4 port
Disconnect
L
L
H
L
L
H
H
X
L
H
X
H
2
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SCDS123A − JULY 2003 − REVISED OCTOBER 2003
logic diagram (positive logic)
7
6
1A
1B1
SW
5
1B2
SW
4
1B3
SW
3
1B4
SW
9
10
2A
2B1
SW
11
2B2
SW
12
2B3
2B4
SW
13
SW
14
S0
2
S1
1
1OE
15
2OE
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
†
EN
†
EN is the internal enable signal applied to the switch.
3
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ꢉꢏ ꢙ ꢅ ꢋ ꢀ ꢀꢚ ꢔ ꢆ ꢄꢛ ꢚ ꢔ ꢆꢛ ꢜ ꢈ ꢏꢙ ꢋꢁ ꢊꢒ ꢗꢀ ꢛꢐ ꢐ ꢆ ꢕꢗ ꢐꢆ ꢒꢄꢆ ꢔ ꢐ ꢁ
SCDS123A − JULY 2003 − REVISED OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN
4
MAX
5.5
5.5
0.8
5.5
85
UNIT
V
V
V
V
V
Supply voltage
CC
High-level control input voltage
Low-level control input voltage
Data input/output voltage
Operating free-air temperature
2
V
IH
0
V
IL
0
V
I/O
T
A
−40
°C
NOTE 7: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS123A − JULY 2003 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Control inputs
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 4.5 V,
= 5 V,
I = −18 mA
IN
−1.8
V
IK
CC
CC
CC
CC
CC
CC
CC
0 mA > I ≥ −50 mA,
I
Data inputs
Switch OFF
Switch OFF,
−2
1
V
IKU
V
V
V
= V
or GND,
IN
IN
O
CC
I
I
I
I
Control inputs
= 5.5 V,
= 5.5 V,
= 0,
= V
or GND
µA
µA
µA
µA
IN
CC
= 0 to 5.5 V,
‡
10
10
3
OZ
off
V = 0,
V
= V or GND
CC
I
IN
V = 0
V
O
= 0 to 5.5 V,
= 0,
= V or GND,
CC
I
I
V
I/O
IN
= 5.5 V,
Switch ON or OFF
CC
§
∆I
Control inputs
Control inputs
A port
V
V
= 5.5 V,
One input at 3.4 V,
Other inputs at V
CC
or GND
2.5
mA
pF
pF
pF
CC
C
C
C
= 3 V or 0
= 3 V or 0,
= 3 V or 0,
3.5
14
in
IN
V
I/O
Switch OFF,
Switch ON,
V
V
= V
= V
or GND
or GND
io(OFF)
io(ON)
IN
CC
B port
5.5
V
V
22
8
pF
I/O
IN
CC
= 4 V,
CC
V = 2.4 V,
I
O
= −15 mA
12
I
TYP at V
CC
= 4 V
¶
I
O
I
O
I
O
= 64 mA
= 30 mA
= −15 mA
3
3
5
6
6
Ω
r
on
V = 0
I
V
CC
= 4.5 V
V = 2.4 V,
I
10
V
†
‡
§
¶
and I refer to control inputs. V , V , I , and I refer to data pins.
IN
IN
I
O
I
O
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
CC
A
For I/O ports, the parameter I
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at the specified voltage level, rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 3)
V
= 5 V
CC
0.5 V
V
= 4 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
#
A or B
B or A
0.24
5.9
6.2
5.7
6.2
0.15
5.4
5.8
5.3
5.8
ns
ns
t
t
pd
S
S
A
B
1.5
1.5
1.5
1.5
pd(s)
t
ns
ns
en
A or B
B
OE
S
t
dis
A or B
5.7
1.5
5.3
OE
#
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉꢏ ꢙ ꢅ ꢋ ꢀ ꢀꢚ ꢔ ꢆ ꢄꢛ ꢚ ꢔ ꢆꢛ ꢜ ꢈ ꢏꢙ ꢋꢁ ꢊꢒ ꢗꢀ ꢛꢐ ꢐ ꢆ ꢕꢗ ꢐꢆ ꢒꢄꢆ ꢔ ꢐ ꢁ
SCDS123A − JULY 2003 − REVISED OCTOBER 2003
undershoot characteristics (see Figures 1 and 2)
†
PARAMETER
TEST CONDITIONS
Switch OFF,
= 5 V (unless otherwise noted), T = 25°C.
MIN
TYP
MAX
UNIT
V
V
CC
= 5.5 V,
V
IN
= V
CC
or GND
2
V
−0.3
V
OUTU
OH
†
All typical values are at V
CC
A
V
CC
11 V
100 kΩ
5.5 V
Input
(Open
Socket)
Input
Generator
90 %
10 %
90 %
10 %
50 Ω
2 ns 2 ns
20 ns
DUT
Ax
Bx
−2 V
100 kΩ
10 pF
V
S
Output
V
OH
V
OH
(V
OUTU
)
− 0.3
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage (V ) and Output
I
Voltage (V
) Waveforms
OUTU
(Switch OFF)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢔ
ꢆ
ꢛ
ꢜ
ꢈ
ꢏ
ꢙ
ꢋ
ꢁ
ꢊ
ꢒ
ꢗ
ꢀ
ꢛ
ꢐ
ꢐ
ꢆ
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ꢔꢐ
SCDS123A − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
7 V
Open
GND
Input Generator
50 Ω
S1
R
V
V
O
L
I
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
∆
C
R
V
CC
TEST
L
L
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
or GND
or GND
50 pF
50 pF
t
pd(s)
5 V 0.5 V
4 V
7 V
7 V
500 Ω
500 Ω
GND
GND
50 pF
50 pF
0.3 V
0.3 V
t
/t
PLZ PZL
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
50 pF
50 pF
0.3 V
0.3 V
t
/t
PHZ PZH
Output
Control
(V
3 V
0 V
1.5 V
1.5 V
)
IN
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
Output
Control
3 V
0 V
1.5 V
V
V
+ V
1.5 V
1.5 V
OL
∆
(V
IN
)
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− V
OH
∆
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
C includes probe and jig capacitance.
L
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
. The tpd propagation delay is the calculated RC time constant of the typical ON-state
pd(s)
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN74CBT3253CD
Status (1)
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CBT3253CDB
SN74CBT3253CDBQR
SN74CBT3253CDBR
SN74CBT3253CDR
SN74CBT3253CPW
SN74CBT3253CPWR
SN74CBT3253CRGYR
SSOP
DB
DBQ
DB
80
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SSOP/
QSOP
2500
2000
2500
90
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SSOP
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SOIC
D
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TSSOP
TSSOP
QFN
PW
PW
RGY
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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Copyright 2005, Texas Instruments Incorporated
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