SN74CBT3253DRG4 [TI]
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER; 1 -OF- 4双FET的复用器/解复用器
| 型号： | SN74CBT3253DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER |
| 文件： | 总16页 (文件大小：721K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉꢇ
ꢊꢋꢌ ꢍ ꢎ ꢏꢐ ꢑꢏ ꢃ ꢑ ꢒꢆ ꢓ ꢋꢍꢆ ꢔꢕ ꢍꢒ ꢖꢒꢗꢘ ꢊꢒꢓ ꢋꢍꢆꢔ ꢕ ꢍꢒ ꢖꢒ ꢗ
SCDS018O − MAY 1995 − REVISED JANUARY 2004
D
TTL-Compatible Input Levels
D, DB, DBQ, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
V
2OE
S0
2B4
2B3
2B2
2B1
2A
1OE
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
1
16
1B4
1B3
1B2
1B1
1A
15
14
13
12
11
10
S1
1B4
1B3
1B2
1B1
1A
2
2OE
S0
2B4
2B3
2B2
2B1
3
4
5
6
7
GND
8
9
description/ordering information
The SN74CBT3253 is a dual 1-of-4 high-speed TTL-compatible FET multiplexer/demultiplexer. The low
on-state resistance of the switch allows connections to be made with minimal propagation delay.
1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
Tape and reel
SN74CBT3253RGYR
SN74CBT3253D
CU253
Tube
SOIC − D
CBT3253
Tape and reel
Tape and reel
SN74CBT3253DR
SN74CBT3253DBR
SN74CBT3253DBQR
SN74CBT3253PW
SN74CBT3253PWR
SSOP − DB
CU253
CU253
−40°C to 85°C
SSOP (QSOP) − DBQ Tape and reel
Tube
TSSOP − PW
CU253
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
FUNCTION
1OE
X
2OE
H
S1
X
X
L
S0
X
X
L
Disconnect 1A and 2A
Disconnect 1A and 2A
1A to 1B1 and 2A to 2B1
1A to 1B2 and 2A to 2B2
1A to 1B3 and 2A to 2B3
1A to 1B4 and 2A to 2B4
H
X
L
L
L
L
L
H
L
L
L
H
H
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇ
ꢊ ꢋꢌꢍ ꢎ ꢏꢐꢑ ꢏꢃ ꢑ ꢒ ꢆ ꢓꢋ ꢍꢆꢔ ꢕ ꢍ ꢒꢖ ꢒꢗ ꢘ ꢊꢒ ꢓꢋ ꢍꢆ ꢔꢕ ꢍꢒ ꢖꢒꢗ
SCDS018O − MAY 1995 − REVISED JANUARY 2004
logic diagram (positive logic)
6
5
7
1A
1B1
1B2
4
3
1B3
1B4
2B1
10
9
2A
11
12
13
2B2
2B3
2B4
14
S0
2
S1
1
1OE
15
2OE
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
K
I/O
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢊꢋꢌ ꢍ ꢎ ꢏꢐ ꢑꢏ ꢃ ꢑ ꢒꢆ ꢓ ꢋꢍꢆ ꢔꢕ ꢍꢒ ꢖꢒꢗꢘ ꢊꢒꢓ ꢋꢍꢆꢔ ꢕ ꢍꢒ ꢖꢒ ꢗ
SCDS018O − MAY 1995 − REVISED JANUARY 2004
recommended operating conditions (see Note 4)
MIN
4
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
V
0.8
85
V
T
A
−40
°C
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN TYP
MAX
−1.2
1
UNIT
V
V
V
V
V
V
= 4.5 V,
= 5 V,
IK
CC
CC
CC
CC
I
I
I
V = 5.5 V or GND
I
µA
µA
mA
pF
I
= 5.5 V,
= 5.5 V,
I
O
= 0,
V = V
I CC
or GND
3
CC
‡
∆I
CC
Control inputs
One input at 3.4 V,
Other inputs at V
CC
or GND
2.5
C
Control inputs
A port
V = 3 V or 0
I
3.5
10
4
i
C
V
O
= 3 V or 0,
= 4.5 V
pF
OE = V
CC
io(OFF)
§
B port
I = 64 mA
I
5
7
7
V = 0
I
I = 30 mA
I
5
V
CC
Ω
r
on
V = 2.4 V,
I
I = 15 mA
I
10
15
†
‡
§
All typical values are at V
CC
= 5 V (unless otherwise noted), T = 25°C.
A
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 5 V
CC
0.5 V
V
= 4 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
¶
A or B
B or A
A or B
0.35
6.6
7.1
7.3
7.9
0.25
6.2
6.3
6.4
7.4
ns
ns
t
t
pd
pd
S
S
1.6
1.3
1.4
1.1
t
A or B
A or B
ns
ns
en
OE
S
t
dis
7.3
2.3
7
OE
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇ
ꢊ ꢋꢌꢍ ꢎ ꢏꢐꢑ ꢏꢃ ꢑ ꢒ ꢆ ꢓꢋ ꢍꢆꢔ ꢕ ꢍ ꢒꢖ ꢒꢗ ꢘ ꢊꢒ ꢓꢋ ꢍꢆ ꢔꢕ ꢍꢒ ꢖꢒꢗ
SCDS018O − MAY 1995 − REVISED JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
Open
7 V
S1
Open
500 Ω
t
pd
/t
/t
From Output
Under Test
t
t
PLZ PZL
GND
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
1.5 V
1.5 V
1.5 V
Input
V
V
+ 0.3 V
OL
(see Note B)
V
OL
OH
0 V
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
1.5 V
Output
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74CBT3253D
ACTIVE
SOIC
D
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT3253DBLE
SN74CBT3253DBQR
OBSOLETE
ACTIVE
SSOP
DB
16
16
TBD
Call TI
Call TI
SSOP/
QSOP
DBQ
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN74CBT3253DBQRE4
SN74CBT3253DBQRG4
SN74CBT3253DBR
SN74CBT3253DBRE4
SN74CBT3253DBRG4
SN74CBT3253DE4
SN74CBT3253DG4
SN74CBT3253DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP/
QSOP
DBQ
DBQ
DB
DB
DB
D
16
16
16
16
16
16
16
16
16
16
16
16
16
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP
SSOP
SSOP
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT3253DRE4
SN74CBT3253DRG4
SN74CBT3253PW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT3253PWE4
SN74CBT3253PWG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT3253PWLE
SN74CBT3253PWR
OBSOLETE TSSOP
PW
PW
16
16
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT3253PWRE4
SN74CBT3253PWRG4
SN74CBT3253RGYR
SN74CBT3253RGYRG4
PW
PW
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
RGY
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2007
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
180
(mm)
0
SN74CBT3253DBQR
SN74CBT3253DBR
SN74CBT3253DR
DBQ
DB
16
16
16
16
16
SITE 27
SITE 41
SITE 27
SITE 41
SITE 41
6.4
8.2
6.5
7.0
3.8
5.2
6.6
2.1
2.5
2.1
1.6
1.5
8
12
8
12
16
16
12
12
Q1
Q1
Q1
Q1
Q1
16
D
16
10.3
5.6
SN74CBT3253PWR
SN74CBT3253RGYR
PW
RGY
12
8
12
4.3
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74CBT3253DBQR
SN74CBT3253DBR
SN74CBT3253DR
DBQ
DB
16
16
16
16
16
SITE 27
SITE 41
SITE 27
SITE 41
SITE 41
342.9
346.0
342.9
346.0
190.5
338.1
346.0
345.9
346.0
212.7
20.64
33.0
D
28.58
29.0
SN74CBT3253PWR
SN74CBT3253RGYR
PW
RGY
31.75
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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