SN74CBT3861PWRG4 [TI]

CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24;
SN74CBT3861PWRG4
型号: SN74CBT3861PWRG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24

驱动 光电二极管 输出元件 逻辑集成电路
文件: 总14页 (文件大小:885K)
中文:  中文翻译
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SN74CBT3861  
10-BIT FET BUS SWITCH  
SCDS061D – APRIL 1998 – REVISED OCTOBER 2000  
DBQ, DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
5-Switch Connection Between Two Ports  
TTL-Compatible Input Levels  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
NC  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
description  
The SN74CBT3861 provides ten bits of  
high-speed TTL-compatible bus switching. The  
low on-state resistance of the switch allows  
connections to be made with minimal propagation  
delay.  
A9 10  
15 B8  
The device is organized as one 10-bit switch with  
a single output-enable (OE) input. When OE is  
low, the switch is on, and port A is connected to  
port B. When OE is high, the switch is open, and  
the high-impedance state exists between the two  
ports.  
A10  
GND  
B9  
B10  
11  
12  
14  
13  
NC – No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube  
SN74CBT3861DW  
SOIC – DW  
CBT3861  
Tape and reel SN74CBT3861DWR  
Tape and reel SN74CBT3861DBQR  
Tape and reel SN74CBT3861PWR  
Tape and reel SN74CBT3861DGVR  
–40°C to 85°C  
SSOP (QSOP) – DBQ  
TSSOP – PW  
CBT3861  
CU861  
TVSOP – DGV  
CU861  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUT  
FUNCTION  
OE  
L
A port = B port  
Disconnect  
H
logic diagram (positive logic)  
2
22  
13  
A1  
A10  
OE  
B1  
11  
23  
B10  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74CBT3861  
10-BIT FET BUS SWITCH  
SCDS061D – APRIL 1998 – REVISED OCTOBER 2000  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA  
IK I/O  
Package thermal impedance, θ (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W  
JA  
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W  
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
recommended operating conditions (see Note 3)  
MIN  
4
MAX  
UNIT  
V
V
V
V
Supply voltage  
5.5  
CC  
IH  
IL  
High-level control input voltage  
Low-level control input voltage  
Operating free-air temperature  
2
V
0.8  
85  
V
T
A
–40  
°C  
NOTE 3: All unused control inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
I = –18 mA  
MIN TYP  
MAX  
–1.2  
±1  
UNIT  
V
V
V
V
V
V
= 4.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
IK  
CC  
CC  
CC  
CC  
I
I
I
V = 5.5 V or GND  
I
µA  
µA  
mA  
pF  
I
I
O
= 0,  
V = V  
I
or GND  
3
CC  
CC  
§
I  
CC  
Control inputs  
One input at 3.4 V,  
Other inputs at V  
or GND  
2.5  
CC  
C
C
Control inputs V = 3 V or 0  
3
5
i
I
V
O
= 3 V or 0,  
OE = V  
pF  
io(OFF)  
CC  
V
= 4 V,  
CC  
V = 2.4 V,  
I
I = 15 mA  
I
14  
22  
TYP at V  
= 4 V  
CC  
I = 64 mA  
I
5
5
7
7
r
on  
V = 0  
I
V
CC  
= 4.5 V  
I = 30 mA  
I
V = 2.4 V,  
I
I = 15 mA  
I
10  
15  
§
All typical values are at V  
= 5 V (unless otherwise noted), T = 25°C.  
A
CC  
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V  
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by  
the lowest voltage of the two (A or B) terminals.  
or GND.  
CC  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74CBT3861  
10-BIT FET BUS SWITCH  
SCDS061D – APRIL 1998 – REVISED OCTOBER 2000  
switching characteristics over recommended operating free-air temperature range (unless  
otherwise noted) (see Figure 1)  
V
= 5 V  
CC  
± 0.5 V  
V
= 4 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
CC  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
0.25  
7.5  
t
t
t
A or B  
OE  
B or A  
A or B  
A or B  
0.35  
8.1  
ns  
ns  
ns  
pd  
3.8  
3.4  
en  
6.3  
6.6  
OE  
dis  
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when  
driven by an ideal voltage source (zero output impedance).  
PARAMETER MEASUREMENT INFORMATION  
7 V  
TEST  
S1  
S1  
Open  
GND  
500 Ω  
t
Open  
7 V  
pd  
/t  
From Output  
Under Test  
t
PLZ PZL  
t
/t  
Open  
PHZ PZH  
C
= 50 pF  
L
500 Ω  
(see Note A)  
3 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
LOAD CIRCUIT  
t
t
PLZ  
PZL  
Output  
Waveform 1  
S1 at 7 V  
3.5 V  
3 V  
0 V  
1.5 V  
Input  
1.5 V  
1.5 V  
V
+ 0.3 V  
OL  
(see Note B)  
V
OL  
OH  
t
t
PHZ  
PZH  
t
t
PHL  
PLH  
Output  
Waveform 2  
S1 at Open  
(see Note B)  
V
V
V
OH  
V
OH  
– 0.3 V  
1.5 V  
Output  
1.5 V  
1.5 V  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
are the same as t  
are the same as t  
.
dis  
en  
.
pd  
PLZ  
PZL  
PLH  
PHZ  
PZH  
PHL  
.
Figure 1. Load Circuit and Voltage Waveforms  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Aug-2013  
PACKAGING INFORMATION  
Orderable Device  
SN74CBT3861DBQR  
SN74CBT3861DBQRE4  
SN74CBT3861DBQRG4  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
ACTIVE  
SSOP  
SSOP  
SSOP  
DBQ  
24  
24  
24  
2500  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
CBT3861  
ACTIVE  
ACTIVE  
DBQ  
DBQ  
2500  
2500  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
CBT3861  
CBT3861  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
SN74CBT3861DGVRE4  
SN74CBT3861DGVRG4  
SN74CBT3861DW  
ACTIVE  
ACTIVE  
ACTIVE  
TVSOP  
TVSOP  
SOIC  
DGV  
DGV  
DW  
24  
24  
24  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
-40 to 85  
-40 to 85  
-40 to 85  
CU861  
TBD  
CU861  
25  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-1-260C-UNLIM  
CBT3861  
SN74CBT3861DWE4  
SN74CBT3861DWG4  
SN74CBT3861DWR  
SN74CBT3861DWRE4  
SN74CBT3861DWRG4  
SN74CBT3861PWR  
SN74CBT3861PWRE4  
SN74CBT3861PWRG4  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
DW  
DW  
DW  
DW  
DW  
PW  
PW  
PW  
24  
24  
24  
24  
24  
24  
24  
24  
25  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
CBT3861  
CBT3861  
CBT3861  
CBT3861  
CBT3861  
CU861  
25  
Green (RoHS  
& no Sb/Br)  
SOIC  
2000  
2000  
2000  
2000  
2000  
2000  
Green (RoHS  
& no Sb/Br)  
SOIC  
Green (RoHS  
& no Sb/Br)  
SOIC  
Green (RoHS  
& no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
CU861  
Green (RoHS  
& no Sb/Br)  
CU861  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Aug-2013  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
12-Aug-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
SN74CBT3861DBQR  
SN74CBT3861DWR  
SN74CBT3861PWR  
SSOP  
SOIC  
DBQ  
DW  
PW  
24  
24  
24  
2500  
2000  
2000  
330.0  
330.0  
330.0  
16.4  
24.4  
16.4  
6.5  
10.75 15.7  
6.95 8.3  
9.0  
2.1  
2.7  
1.6  
8.0  
12.0  
8.0  
16.0  
24.0  
16.0  
Q1  
Q1  
Q1  
TSSOP  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
12-Aug-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
SN74CBT3861DBQR  
SN74CBT3861DWR  
SN74CBT3861PWR  
SSOP  
SOIC  
DBQ  
DW  
PW  
24  
24  
24  
2500  
2000  
2000  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
38.0  
45.0  
38.0  
TSSOP  
Pack Materials-Page 2  
MECHANICAL DATA  
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000  
DGV (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
24 PINS SHOWN  
0,23  
0,13  
M
0,07  
0,40  
24  
13  
0,16 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
0°ā8°  
0,75  
1
12  
0,50  
A
Seating Plane  
0,08  
0,15  
0,05  
1,20 MAX  
PINS **  
14  
16  
20  
24  
38  
48  
56  
DIM  
A MAX  
A MIN  
3,70  
3,50  
3,70  
3,50  
5,10  
4,90  
5,10  
4,90  
7,90  
7,70  
9,80  
9,60  
11,40  
11,20  
4073251/E 08/00  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.  
D. Falls within JEDEC: 24/48 Pins – MO-153  
14/16/20/56 Pins – MO-194  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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