SN74CBT6800CDGVRE4 [TI]

具有 –2V 下冲保护的 5V、1:1 (SPST)、10 通道通用 FET 总线开关 | DGV | 24 | -40 to 85;


型号：	SN74CBT6800CDGVRE4
厂家：	TEXAS INSTRUMENTS
描述：	具有 –2V 下冲保护的 5V、1:1 (SPST)、10 通道通用 FET 总线开关 \| DGV \| 24 \| -40 to 85 开关
文件：	总16页 (文件大小：459K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉꢄ

ꢊ ꢉ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢒꢓꢎ ꢄꢑꢔꢓ ꢕꢎ ꢖ ꢗ ꢏꢆ ꢒ ꢏꢆꢀ

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SCDS138 − OCTOBER 2003

Member of the Texas Instruments

Widebus Family

Undershoot Protection for Off-Isolation on

A and B Ports Up to −2 V

Operating Range From 4 V to 5.5 V

Data I/Os Support 0 to 5-V Signaling Levels

(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)

Control Inputs Can be Driven by TTL or

5-V/3.3-V CMOS Outputs

B-Port Outputs Are Precharged by Bias

Voltage (BIASV) to Minimize Signal

Distortion During Live Insertion and

Hot-Plugging

Supports Partial-Power-Down Mode

off

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Supports PCI Hot Plug

Bidirectional Data Flow, With Near-Zero

Propagation Delay

ESD Performance Tested Per JESD 22

− 2000-V Human-Body Model

(A114-B, Class II)

Low ON-State Resistance (r

)

Characteristics (r = 3 Ω Typical)

− 1000-V Charged-Device Model (C101)

Low Input/Output Capacitance Minimizes

Loading and Signal Distortion

Supports Both Digital and Analog

Applications: PCI Interface, Memory

Interleaving, Bus Isolation, Low-Distortion

Signal Gating

= 5.5 pF Typical)

io(OFF)

Data and Control Inputs Provide

Undershoot Clamp Diodes

Low Power Consumption

= 3 µA Max)

DB, DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

A10

GND

B10

BIASV

description/ordering information

The SN74CBT6800C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),

allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the

SN74CBT6800C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring

that the switch remains in the proper OFF state. The device also precharges the B port to a user-selectable bias

voltage (BIASV) to minimize live-insertion noise.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢉ ꢄ

ꢊꢉ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅ ꢏꢀ ꢀ ꢐꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢒ ꢓꢎ ꢄꢑ ꢔꢓꢕ ꢎꢖ ꢗ ꢏꢆ ꢒꢏꢆ ꢀ

ꢘꢋ ꢙ ꢅ ꢏꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢚꢛ ꢋꢙ ꢏꢁ ꢖꢎ ꢓꢀ ꢑꢗ ꢗ ꢆ ꢒꢓꢗ ꢆ ꢎꢄ ꢆꢌ ꢗ ꢁ

SCDS138 − OCTOBER 2003

description/ordering information (continued)

The SN74CBT6800C is a 10-bit bus switch with a single output-enable (ON) input. When ON is low, the 10-bit

bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When

ON is high, the 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. The

B port is precharged to BIASV through the equivalent of a 10-kΩ resistor when ON is high, or if the device is

powered down (V

= 0 V).

During insertion (or removal) of a card into (or from) an active bus, the card’s output voltage may be close to

GND. When the connector pins make contact, the card’s parasitic capacitance tries to force the bus signal to

GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch

with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers

on the active bus. This method will ensure that any glitch produced by insertion (or removal) of the card will not

cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise.

This device is fully specified for partial-power-down applications using I . The I feature ensures that

off

damaging current will not backflow through the device when it is powered down. The device has isolation during

power off.

To ensure the high-impedance state during power up or power down, ON should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

Tube

SN74CBT6800CDW

SN74CBT6800CDWR

SN74CBT6800CDB

SN74CBT6800CDBR

SN74CBT6800CDBQR

SN74CBT6800CPW

SN74CBT6800CPWR

SN74CBT6800CDGVR

SOIC − DW

SSOP − DB

CBT6800C

Tape and reel

Tube

CT6800C

Tape and reel

Tube

−40°C to 85°C

SSOP (QSOP) − DBQ

CBT6800C

TSSOP − PW

TVSOP − DGV

CT6800C

Tape and reel

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

INPUT INPUT/OUTPUT

FUNCTION

A port = B port

Disconnect

B port = BIASV

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉꢄ

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ꢘ ꢋꢙ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢚꢛ ꢋꢙ ꢏꢁꢖ ꢎꢓꢀꢑ ꢗꢗ ꢆ ꢒꢓ ꢗ ꢆꢎ ꢄꢆ ꢌꢗ ꢁ

SCDS138 − OCTOBER 2003

logic diagram (positive logic)

BIASV

A10

B10

simplified schematic, each FET switch (SW)

Undershoot

Protection Circuit

†

EN is the internal enable signal applied to the switch.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢉ ꢄ

ꢊꢉ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅ ꢏꢀ ꢀ ꢐꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢒ ꢓꢎ ꢄꢑ ꢔꢓꢕ ꢎꢖ ꢗ ꢏꢆ ꢒꢏꢆ ꢀ

ꢘꢋ ꢙ ꢅ ꢏꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢚꢛ ꢋꢙ ꢏꢁ ꢖꢎ ꢓꢀ ꢑꢗ ꢗ ꢆ ꢒꢓꢗ ꢆ ꢎꢄ ꢆꢌ ꢗ ꢁ

SCDS138 − OCTOBER 2003

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Bias supply voltage range, BIASV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I/O

Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

IK IN

I/OK I/O

I/O port clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

I/O

Continuous current through V

or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Package thermal impedance, θ (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W

DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to ground unless otherwise specified.

2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. V and V are used to denote specific conditions for V

I/O

4. I and I are used to denote specific conditions for I .

I/O

5. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 6)

MIN

MAX

UNIT

Supply voltage

5.5

BIASV Bias supply voltage

5.5

High-level control input voltage

Low-level control input voltage

Data input/output voltage

0.8

5.5

I/O

Operating free-air temperature

−40

°C

NOTE 6: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004. BIASV is a supply voltage, not a control input.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉꢄ

ꢊ ꢉ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢒꢓ ꢎꢄꢑꢔꢓ ꢕꢎ ꢖ ꢗ ꢏꢆ ꢒꢏ ꢆꢀ

ꢘ ꢋꢙ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢚꢛ ꢋꢙ ꢏꢁꢖ ꢎꢓꢀꢑ ꢗꢗ ꢆ ꢒꢓ ꢗ ꢆꢎ ꢄꢆ ꢌꢗ ꢁ

SCDS138 − OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

Control inputs

TEST CONDITIONS

MIN TYP

MAX

UNIT

= 4.5 V,

= 5 V,

I = −18 mA

−1.8

0 mA > I ≥ −50 mA,

Data inputs

Switch OFF

−2

IKU

= V

or GND,

I = −10 mA,

‡

= BIASV = 5 V,

O(USP)

= V

or GND,

= 0 V,

BIASV = V ,

I = 0

V −0.1

B port

Control inputs

= 5.5 V,

V = V

IN CC

or GND

µA

BIASV = 2.4 V,

Switch OFF,

V = V or GND

B port

= 4.5 V,

0.25

= 0,

Switch OFF,

V = V or GND

= 0 to 5.5 V,

= 5.5 V,

= 0,

µA

V = 0,

V = 0

= 0 to 5.5 V,

= 0,

= V or GND,

off

I/O

= 5.5 V,

Switch ON or OFF

∆I

Control inputs

A port

= 5.5 V,

One input at 3.4 V,

Other inputs at V

or GND

2.5

= 3 V or 0

= 3 V or 0,

5.5

Switch OFF,

Switch ON,

= V

or GND

io(OFF)

io(ON)

I/O

13.5

= 4 V,

V = 2.4 V,

= −15 mA

TYP at V

= 4 V

= 64 mA

= 30 mA

= −15 mA

Ω

V = 0

= 4.5 V

V = 2.4 V,

†

‡

and I refer to control inputs. V , V , I , and I refer to data pins.

All typical values are at V

= 5 V (unless otherwise noted), T = 25°C.

= A-port undershoot static protection.

O(USP)

For I/O ports, the parameter I

includes the input leakage current.

This is the increase in supply current for each input that is at the specified voltage level, rather than V

or GND.

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by

the lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)

= 5 V

0.5 V

= 4 V

TEST

CONDITIONS

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

MAX

MIN

MAX

A or B

B or A

A or B

0.24

6.2

5.6

0.15

5.9

6.2

1.5

BIASV = GND

BIASV = 3 V

BIASV = GND

BIASV = 3 V

PZH

PZL

PHZ

PLZ

A or B

The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,

when driven by an ideal voltage source (zero output impedance).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢉ ꢄ

ꢊꢉ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅ ꢏꢀ ꢀ ꢐꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢒ ꢓꢎ ꢄꢑ ꢔꢓꢕ ꢎꢖ ꢗ ꢏꢆ ꢒꢏꢆ ꢀ

ꢘꢋ ꢙ ꢅ ꢏꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢚꢛ ꢋꢙ ꢏꢁ ꢖꢎ ꢓꢀ ꢑꢗ ꢗ ꢆ ꢒꢓꢗ ꢆ ꢎꢄ ꢆꢌ ꢗ ꢁ

SCDS138 − OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

Input Generator

50 Ω

TEST CIRCUIT

DUT

7 V

Open

GND

Input Generator

50 Ω

(see Note A)

∆

TEST

5 V 0.5 V

4 V

Open

500 Ω

or GND

50 pF

pd(s)

5 V 0.5 V

4 V

7 V

500 Ω

GND

50 pF

0.3 V

PLZ PZL

5 V 0.5 V

4 V

Open

500 Ω

50 pF

0.3 V

PHZ PZH

Output

Control

3 V

0 V

1.5 V

)

PLZ

PZL

Output

Waveform 1

S1 at 7 V

3.5 V

Output

Control

3 V

0 V

1.5 V

+ V

1.5 V

∆

)

(see Note B)

PZH

PHZ

PLH

PHL

Output

Waveform 2

S1 at Open

(see Note B)

− V

∆

1.5 V

Output

1.5 V

0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (t

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

)

pd(s)

C includes probe and jig capacitance.

NOTES: A.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

and t

are the same as t

PLZ

PZL

PLH

PHZ

PZH

PHL

dis

. The tpd propagation delay is the calculated RC time constant of the typical ON-state

pd(s)

resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN74CBT6800CDGVR

SN74CBT6800CDGVRE4

SN74CBT6800CDWR

SN74CBT6800CPWR

ACTIVE

TVSOP

SOIC

DGV

2000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 85

CT6800C

NIPDAU

CT6800C

CBT6800C

CT6800C

TSSOP

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74CBT6800CDGVR TVSOP

DGV

2000

330.0

12.4

24.4

16.4

6.9

10.75 15.7

6.95 8.3

5.6

1.6

2.7

1.6

8.0

12.0

8.0

12.0

24.0

16.0

SN74CBT6800CDWR

SN74CBT6800CPWR

SOIC

TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74CBT6800CDGVR

SN74CBT6800CDWR

SN74CBT6800CPWR

TVSOP

SOIC

DGV

2000

367.0

350.0

367.0

350.0

367.0

35.0

43.0

38.0

TSSOP

Pack Materials-Page 2

PACKAGE OUTLINE

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

22X 0.65

7.15

7.9

7.7

NOTE 3

0.30

24X

4.5

4.3

NOTE 4

0.19

1.2 MAX

0.1

C A B

0.25

GAGE PLANE

0.15

0.05

(0.15) TYP

SEE DETAIL A

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220208/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

24X (1.5)

(R0.05) TYP

24X (0.45)

22X (0.65)

SYMM

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220208/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

24X (1.5)

SYMM

(R0.05) TYP

24X (0.45)

22X (0.65)

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220208/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

0,07

0,40

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

0,50

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74CBT6800CDGVRE4 [TI]

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