SN74CBTD3305CPW [TI]
DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5-V BUS SWITCH WITH - 2-V UNDERSHOOT PROTECTION; 2 -V冲保护 - 通过电平转换， 5 -V BUS开关，双FET总线开关
| 型号： | SN74CBTD3305CPW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5-V BUS SWITCH WITH - 2-V UNDERSHOOT PROTECTION |
| 文件： | 总12页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢈ ꢉꢊ ꢄ
ꢇꢋꢌ ꢍ ꢎ ꢏꢆ ꢅꢋꢀ ꢀꢐ ꢑ ꢆꢄ ꢒ ꢐ ꢑꢆ ꢒ ꢍ ꢏꢓꢏ ꢍ ꢀ ꢒꢑ ꢎꢆ ꢑꢁ ꢔ
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SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003
D
D
D
D
D
Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
D
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
Integrated Diode to V
Down To 3.3-V Output Level Shift
Provides 5-V Input
D
D
D
D
Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
CC
Bidirectional Data Flow, With Near-Zero
Propagation Delay
I
Supports Partial-Power-Down Mode
off
Operation
Low ON-State Resistance (r
)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
on
Characteristics (r = 3 Ω Typical)
on
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
(C
= 5 pF Typical)
io(OFF)
− 1000-V Charged-Device Model (C101)
D
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
D
Supports Both Digital and Analog
Applications: USB Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
V
Operating Range From 4.5 V to 5.5 V
CC
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
1OE
1A
1B
8
7
6
5
V
CC
2OE
2B
2A
GND
description/ordering information
The SN74CBTD3305C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),
on
allowing for minimal propagation delay. This device features an integrated diode in series with V
to provide
CC
level shifting for 5-V input down to 3.3-V output levels. Active Undershoot-Protection Circuitry on the A and B
ports of the SN74CBTD3305C provides protection for undershoot up to −2 V by sensing an undershoot event
and ensuring that the switch remains in the proper OFF state.
The SN74CBTD3305C is organized as two 1-bit bus switches with separate output-enable (1OE, 2OE) inputs.
It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is high, the associated 1-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is low, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
Tube
SN74CBTD3305CD
SOIC − D
CC305C
Tape and reel SN74CBTD3305CDR
Tube SN74CBTD3305CPW
Tape and reel SN74CBTD3305CPWR
−40°C to 85°C
TSSOP − PW
CC305C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
FUNCTION TABLE
(each bus switch)
INPUT INPUT/OUTPUT
FUNCTION
OE
H
A
B
Z
A port = B port
Disconnect
L
logic diagram (positive logic)
2
1
3
1A
1B
SW
SW
1OE
5
7
6
2A
2B
2OE
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
†
EN
†
EN is the internal enable signal applied to the switch.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢈ ꢉꢊ ꢄ
ꢇꢋꢌ ꢍ ꢎ ꢏꢆ ꢅꢋꢀ ꢀꢐ ꢑ ꢆꢄ ꢒ ꢐ ꢑꢆ ꢒ ꢍ ꢏꢓꢏ ꢍ ꢀ ꢒꢑ ꢎꢆ ꢑꢁ ꢔ
ꢊ ꢕꢓ ꢅꢋꢀ ꢀꢐ ꢑ ꢆꢄ ꢒ ꢐ ꢑꢆ ꢒ ꢖ ꢗ ꢕꢓ ꢋꢁꢇ ꢏꢘꢀꢒ ꢙꢙ ꢆ ꢚꢘꢙ ꢆꢏ ꢄ ꢆꢑ ꢙ ꢁ
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Notes 6 and 7)
MIN
4.5
2
MAX
5.5
5.5
0.8
5.5
85
UNIT
V
V
V
V
V
Supply voltage
CC
High-level control input voltage
Low-level control input voltage
Data input/output voltage
Operating free-air temperature
V
IH
0
V
IL
0
V
I/O
T
A
−40
°C
NOTES: 6. All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7. In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no
level-shifting effect.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Control inputs
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
= 4.5 V,
= 5 V,
I = −18 mA
IN
−1.8
V
IK
CC
0 mA > I ≥ −50 mA,
I
Data inputs
Switch OFF
−2
V
IKU
OH
CC
V
IN
= V
or GND,
CC
See Figures 4 and 5
I
I
I
I
Control inputs
V
V
V
V
= 5.5 V,
= 5.5 V,
= 0,
V
V
= V
or GND
1
10
µA
µA
µA
mA
IN
CC
CC
CC
CC
CC
IN
CC
= 0 to 5.5 V,
Switch OFF,
O
‡
OZ
off
V = 0,
I
V
= V or GND
CC
IN
V = 0
V
O
= 0 to 5.5 V,
= 0,
= V or GND,
CC
10
I
I
V
I/O
IN
= 5.5 V,
Switch ON or OFF
1.5
2.5
CC
§
∆I
Control inputs
Control inputs
V
V
V
V
= 5.5 V,
One input at 3.4 V,
Other inputs at V
CC
or GND
mA
pF
pF
pF
CC
C
C
C
= 3 V or 0
= 3 V or 0,
= 3 V or 0,
3.5
5
in
IN
Switch OFF,
Switch ON,
V
V
= V
= V
or GND
or GND
io(OFF)
io(ON)
I/O
I/O
IN
CC
12.5
IN
CC
I
O
I
O
I
O
= 64 mA
= 30 mA
3
3
8
6
6
V = 0
I
¶
V
CC
= 4.5 V
Ω
r
on
V = 2.4 V,
I
= −15 mA
20
V
†
‡
§
¶
and I refer to control inputs. V , V , I , and I refer to data pins.
IN
IN
I
O
I
O
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
CC
A
For I/O ports, the parameter I
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at the specified voltage level, rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
V
= 5 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
#
t
t
t
A or B
OE
B or A
A or B
A or B
0.15
4.7
ns
ns
ns
pd
en
1.5
1.5
5.3
OE
dis
#
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢈ ꢉꢊ ꢄ
ꢇꢋꢌ ꢍ ꢎ ꢏꢆ ꢅꢋꢀ ꢀꢐ ꢑ ꢆꢄ ꢒ ꢐ ꢑꢆ ꢒ ꢍ ꢏꢓꢏ ꢍ ꢀ ꢒꢑ ꢎꢆ ꢑꢁ ꢔ
ꢊ ꢕꢓ ꢅꢋꢀ ꢀꢐ ꢑ ꢆꢄ ꢒ ꢐ ꢑꢆ ꢒ ꢖ ꢗ ꢕꢓ ꢋꢁꢇ ꢏꢘꢀꢒ ꢙꢙ ꢆ ꢚꢘꢙ ꢆꢏ ꢄ ꢆꢑ ꢙ ꢁ
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003
undershoot characteristics (see Figures 1 and 2)
†
PARAMETER
TEST CONDITIONS
Switch OFF,
= 5 V (unless otherwise noted), T = 25°C.
MIN
TYP
MAX
UNIT
V
V
CC
= 5.5 V,
V
IN
= V
CC
or GND
2
V
−0.3
V
OUTU
OH
†
All typical values are at V
CC
A
V
CC
11 V
100 kΩ
5.5 V
Input
(Open
Socket)
Input
Generator
90 %
10 %
90 %
10 %
50 Ω
2 ns 2 ns
20 ns
DUT
Ax
Bx
−2 V
100 kΩ
10 pF
V
S
Output
V
OH
V
OH
(V
OUTU
)
− 0.3
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage (V ) and Output
I
Voltage (V
) Waveforms
OUTU
(Switch OFF)
5
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SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
FOR LEVEL SHIFTER
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
7 V
Open
GND
Input Generator
50 Ω
S1
R
V
V
O
L
I
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
C
R
V
TEST
pd(s)
/t
∆
L
L
CC
t
5 V 0.5 V
5 V 0.5 V
5 V 0.5 V
Open
7 V
500 Ω
500 Ω
500 Ω
V
CC
or GND
50 pF
50 pF
50 pF
t
PLZ PZL
GND
0.3 V
0.3 V
t
/t
PHZ PZH
Open
V
CC
Output
Control
(V
3 V
0 V
1.5 V
1.5 V
)
IN
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
Output
Control
3 V
0 V
1.5 V
V
V
+ V
1.5 V
1.5 V
OL
∆
(V
IN
)
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− V
OH
∆
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
C includes probe and jig capacitance.
L
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
. The tpd propagation delay is the calculated RC time constant of the typical ON-state
pd(s)
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢈ ꢉꢊ ꢄ
ꢇꢋꢌ ꢍ ꢎ ꢏꢆ ꢅꢋꢀ ꢀꢐ ꢑ ꢆꢄ ꢒ ꢐ ꢑꢆ ꢒ ꢍ ꢏꢓꢏ ꢍ ꢀ ꢒꢑ ꢎꢆ ꢑꢁ ꢔ
ꢊ ꢕꢓ ꢅꢋꢀ ꢀꢐ ꢑ ꢆꢄ ꢒ ꢐ ꢑꢆ ꢒ ꢖ ꢗ ꢕꢓ ꢋꢁꢇ ꢏꢘꢀꢒ ꢙꢙ ꢆ ꢚꢘꢙ ꢆꢏ ꢄ ꢆꢑ ꢙ ꢁ
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH
OUTPUT VOLTAGE HIGH
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4
3.75
3.5
4
3.75
3.5
T
= 85°C
CC
T = 25°C
A
A
I
V = V
V = V
I
CC
100 µA
100 µA
6 mA
12 mA
6 mA
12 mA
3.25
3.25
24 mA
24 mA
3
3
2.75
2.75
2.5
2.25
2
2.5
2.25
2
1.75
1.5
1.75
1.5
4.5
4.75
V
5
5.25
5.5
5.75
4.5
4.75
5
5.25
− Supply Voltage − V
CC
5.5
5.75
− Supply Voltage − V
V
CC
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4
T
= 0°C
CC
A
I
3.75
3.5
V = V
100 µA
3.25
6 mA
12 mA
3
24 mA
2.75
2.5
2.25
2
1.75
1.5
4.5
4.75
5
5.25
5.5
5.75
V
CC
− Supply Voltage − V
Figure 4. V
Values
OH
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢇ
ꢁ
ꢋ
ꢓ
ꢂ
ꢌ
ꢅ
ꢃ
ꢍ
ꢄ
ꢎ
ꢋ
ꢅ
ꢏ
ꢀ
ꢆ
ꢆ
ꢀ
ꢇ
ꢅ
ꢐ
ꢈ
ꢈ
ꢋ
ꢆ
ꢉ
ꢀ
ꢄ
ꢊ
ꢄ
ꢀ
ꢒ
ꢐ
ꢐ
ꢑ
ꢑ
ꢆ
ꢆ
ꢄ
ꢒ
ꢒ
ꢖ
ꢐ
ꢑ
ꢆ
ꢋ
ꢒ
ꢁ
ꢍ
ꢇ
ꢏ
ꢏ
ꢓ
ꢘ
ꢏ
ꢀ
ꢍ
ꢀ
ꢒ
ꢑ
ꢎ
ꢆ
ꢑ
ꢁ
ꢔ
ꢊ
ꢕ
ꢑ
ꢗ
ꢕ
ꢓ
ꢒ
ꢙ
ꢙ
ꢆ
ꢚ
ꢘ
ꢙ
ꢆ
ꢏ
ꢄ
ꢆꢑ
ꢙ
ꢁ
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
3.5
3
V
T
A
= 5 V
= 25°C
CC
100 µA
6 mA
12 mA
24 mA
2.5
2
1.5
1
5
0
0
1
2
3
4
5
V − Input Voltage − V
I
Figure 5. Data Output Voltage vs Data Input Voltage
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN74CBTD3305CD
SN74CBTD3305CDR
SN74CBTD3305CPW
SN74CBTD3305CPWR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SOIC
D
2500
150
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TSSOP
TSSOP
PW
PW
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Copyright 2005, Texas Instruments Incorporated
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