SN74CBTD3861PWR [TI]
10-BIT FET BUS SWITCH WITH LEVEL SHIFTING; 与电平转换10位FET总线开关
| 型号： | SN74CBTD3861PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-BIT FET BUS SWITCH WITH LEVEL SHIFTING |
| 文件： | 总6页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBTD3861
10-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS084G – JULY 1998 – REVISED JULY 2002
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Designed to Be Used in Level-Shifting
Applications
NC
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
OE
B1
B2
B3
B4
B5
B6
B7
description/ordering information
The SN74CBTD3861 provides ten bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay. A diode to V
is integrated on the die to
CC
A9 10
15 B8
allow for level shifting from 5-V signals at the
device inputs to 3.3-V signals at the device
outputs.
A10
GND
B9
B10
11
12
14
13
The device is organized as one 10-bit switch with
a single output-enable (OE) input. When OE is
low, the switch is on, and port A is connected to
port B. When OE is high, the switch is open, and
the high-impedance state exists between the two
ports.
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74CBTD3861DW
SN74CBTD3861DWR
SN74CBTD3861DBR
SN74CBTD3861DBQR
SN74CBTD3861PWR
SN74CBTD3861DGVR
SOIC – DW
SSOP – DB
CBTD3861
Tape and reel
Tape and reel
CC861
–40°C to 85°C
SSOP (QSOP) – DBQ Tape and reel
CBTD3861
CC861
TSSOP – PW
TVSOP – DGV
Tape and reel
Tape and reel
CC861
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUT
FUNCTION
OE
L
A port = B port
Disconnect
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD3861
10-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS084G – JULY 1998 – REVISED JULY 2002
logic diagram (positive logic)
2
22
13
A1
A10
OE
B1
11
23
B10
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK I/O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
JA
DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
V
0.8
85
V
T
A
–40
°C
In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting
effect.
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD3861
10-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS084G – JULY 1998 – REVISED JULY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
= 4.5 V,
–1.2
V
IK
CC
See Figure 2
I
OH
I
I
V
V
V
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 5.5 V or GND
±1
1.5
2.5
µA
mA
mA
pF
I
CC
CC
CC
I
I
O
= 0,
V = V
or GND
CC
I
CC
‡
∆I
CC
Control inputs
Control inputs
One input at 3.4 V,
Other inputs at V
or GND
CC
C
C
V = 3 V or 0
I
2.5
4
i
V
O
= 3 V or 0,
= 4.5 V
OE = V
CC
pF
io(OFF)
I = 64 mA
I
5
7
7
V = 0
I
§
r
V
CC
I = 30 mA
I
5
Ω
on
V = 2.4 V,
I
I = 15 mA
I
20
50
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
¶
t
t
t
A or B
OE
B or A
A or B
A or B
0.35
10
6
ns
ns
ns
pd
2.6
1
en
OE
dis
¶
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD3861
10-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS084G – JULY 1998 – REVISED JULY 2002
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
TEST
S1
S1
500 Ω
t
Open
7 V
From Output
Under Test
pd
t
/t
PLZ PZL
t
/t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
OL
V
(see Note B)
OL
OH
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
V
OH
V
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD3861
10-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS084G – JULY 1998 – REVISED JULY 2002
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH
OUTPUT VOLTAGE HIGH
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4
3.75
3.5
4
3.75
3.5
T
A
= 85°C
T = 25°C
A
100 µA
100 µA
6 mA
12 mA
6 mA
12 mA
3.25
3.25
24 mA
24 mA
3
3
2.75
2.75
2.5
2.25
2
2.5
2.25
2
1.75
1.5
1.75
1.5
4.5
4.75
V
5
5.25
5.5
5.75
4.5
4.75
5
5.25
5.5
5.75
– Supply Voltage – V
V
CC
– Supply Voltage – V
CC
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4
T
A
= 0°C
3.75
3.5
100 µA
3.25
6 mA
12 mA
3
24 mA
2.75
2.5
2.25
2
1.75
1.5
4.5
4.75
5
5.25
5.5
5.75
V
CC
– Supply Voltage – V
Figure 2. V
Values
OH
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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