SN74CBTH3383DBLE [TI]
CBT/FST/QS/5C/B SERIES, 10-BIT EXCHANGER, TRUE OUTPUT, PDSO24, ssop-24;
| 型号： | SN74CBTH3383DBLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CBT/FST/QS/5C/B SERIES, 10-BIT EXCHANGER, TRUE OUTPUT, PDSO24, ssop-24 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总5页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBTH3383
10-BIT FET BUS-EXCHANGE SWITCH
WITH BUS HOLD
SCDS023G – MAY 1995 – REVISED OCTOBER 1998
DB, DW, OR PW PACKAGE
(TOP VIEW)
Functionally Equivalent to QS3388
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
V
1
24
23
22
21
20
19
18
17
16
BE
1B1
1A1
1A2
1B2
2B1
2A1
2A2
2B2
3B1
3A1
GND
CC
5B2
5A2
5A1
5B1
4B2
4A2
4A1
4B1
2
Bus Hold on Data Inputs/Outputs
Eliminates the Need for External
Pullup/Pulldown Resistors
3
4
5
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
6
7
8
9
10
11
12
15 3B2
description
3A2
BX
14
13
The SN74CBTH3383 provides ten bits of
high-speed TTL-compatible bus switching or
exchanging with bus hold on all I/Os. The low
on-state resistance of the switch allows
connection to be made with minimal propagation
delay.
The device operates as a 10-bit bus switch or a 5-bit bus exchanger, which provides swapping of the A and B
pairs of signals. The bus-exchange function is selected when BE is low. The switches are open when BE is high.
Active bus-hold circuitry is provided to hold unused or floating data inputs/outputs at a valid logic level.
When the switch is turned off, the bus-hold circuit pulls all I/Os to V
or to GND, depending on the last-known
CC
state of the pin. The bus-hold feature is active only when the SN74CBTH3383 I/Os are in the high-impedance
state.
The SN74CBTH3383 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
FUNCTION
BE
BX
A1 PORT A2 PORT
A1 port = B1 port
A2 port = B2 port
L
L
L
B1 port
B2 port
Z
B2 port
B1 port
Z
A2 port = B2 port
A2 port = B1 port
H
X
Disconnect
All ports = bus hold
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTH3383
10-BIT FET BUS-EXCHANGE SWITCH
WITH BUS HOLD
SCDS023G – MAY 1995 – REVISED OCTOBER 1998
logic diagram (positive logic)
3
2
5
1A1
1B1
1B2
4
1A2
21
20
23
5A1
5B1
5B2
22
5A2
1
BE
13
BX
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DD
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK I/O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTH3383
10-BIT FET BUS-EXCHANGE SWITCH
WITH BUS HOLD
SCDS023G – MAY 1995 – REVISED OCTOBER 1998
recommended operating conditions (see Note 3)
MIN
4
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
V
0.8
85
V
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
±1
UNIT
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 5.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
IK
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
V = 5.5 V or GND
I
µA
µA
µA
µA
µA
µA
mA
pF
‡
I
V = 0.8 V
I
100
–100
500
BHL
BHH
§
I
V = 2 V
I
¶
I
V = 0 to 5.5 V
I
BHLO
#
I
V = 0 to 5.5 V
I
–500
BHHO
CC
I
I
O
= 0,
V = V
I
or GND
3
CC
||
∆I
Control inputs
One input at 3.4 V,
Other inputs at V
or GND
CC
2.5
CC
C
C
Control inputs V = 3 V or 0
3
6
i
I
V
O
= 3 V or 0,
BE = V
pF
io(OFF)
CC
V
= 4 V,
CC
V = 2.4,
I
I = 15 mA
I
16
22
TYP at V
= 4 V
CC
I = 64 mA
I
5
5
7
7
Ω
r
on
V = 0
I
V
CC
= 4.5 V,
I = 30 mA
I
V = 2.4 V,
I
I = 15 mA
I
10
15
†
‡
All typical values are at V
The bus hold circuit can sink at least the minimum low sustaining current at V max. I
= 5 V (unless otherwise noted), T = 25°C.
A
CC
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
§
The bus hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 5 V
CC
± 0.5 V
V
= 4 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
MIN
MAX
0.25
9.2
t
t
t
t
A or B
BX
B or A
A or B
A or B
A or B
0.35
10.2
9.6
ns
ns
ns
ns
pd
pd
en
dis
1
1
1
BE
8.6
BE
8.5
7.5
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTH3383
10-BIT FET BUS-EXCHANGE SWITCH
WITH BUS HOLD
SCDS023G – MAY 1995 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
S1
S1
500 Ω
t
pd
/t
Open
7 V
From Output
Under Test
t
GND
PLZ PZL
t
/t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
3 V
0 V
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PZL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
OL
+ 0.3 V
(see Note B)
V
OL
t
PHZ
t
t
PHL
PZH
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
V
OH
– 0.3 V
0 V
1.5 V
Output
1.5 V
1.5 V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
C includes probe and jig capacitance.
L
ENABLE AND DISABLE TIMES
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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