SN74CBTK16245DGGR [TI]
16-BIT FET BUS SWITCH WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT; 与有源钳位冲保护电路， 16位FET总线开关
| 型号： | SN74CBTK16245DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT FET BUS SWITCH WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT |
| 文件： | 总12页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
DGG, DGV, OR DL PACKAGE
Member of the Texas Instruments
Widebus Family
(TOP VIEW)
Standard ’16245-Type Pinout
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
3
4
I
Supports Partial-Power-Down Mode
off
5
Operation
6
Active-Clamp Undershoot-Protection
Circuit on the I/Os Clamps Undershoots up
to –2 V
7
V
V
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
V
V
The SN74CBTK16245 device provides 16 bits of
high-speed TTL-compatible bus switching in a
standard ’16245 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
CC
CC
2B5
2B6
GND
2B7
2B8
NC
2A5
2A6
GND
2A7
2A8
2OE
The A and B ports have an active-clamp
undershoot-protection circuit. When there is an
undershoot, the active-clamp circuit is enabled,
NC – No internal connection
and current from V
is supplied to clamp the
CC
output, preventing the pass transistor from
turning on.
The device is organized as two 8-bit low-impedance switches with separate output-enable (OE) inputs. When OE is
low, the switch is on, and data can flow from the A port to the B port, or vice versa. When OE is high, the switch
is open, and the high-impedance state exists between the two ports.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74CBTK16245DL
SSOP – DL
CBTK16245
Tape and reel
SN74CBTK16245DLR
SN74CBTK16245DGGR
SN74CBTK16245DGVR
–40°C to 85°C
TSSOP – DGG Tape and reel
TVSOP – DGV Tape and reel
CBTK16245
CP245
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
FUNCTION TABLE
(each 8-bit bus switch)
INPUT
FUNCTION
OE
L
A port = B port
Disconnect
H
logic diagram (positive logic)
V
CC
V
CC
†
†
UC
UC
47
2
1A1
1B1
1B8
V
V
CC
CC
†
†
UC
UC
37
48
12
1A8
1OE
V
CC
V
CC
†
†
UC
UC
36
13
23
2A1
2B1
2B8
V
V
CC
CC
†
†
UC
UC
26
25
2A8
2OE
†
Undershoot clamp
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK I/O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
4
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
V
0.8
85
V
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
–2
UNIT
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 5.5 V,
= 0,
IK
CC
CC
CC
CC
CC
CC
CC
I
0 mA ≥ I ≥ –50 mA,
OE = 5.5 V
V
IKU
I
V = 5.5 V
I
10
I
I
µA
= 5.5 V,
= 0,
V = 5.5 V or GND
I
±1
I
I
V or V = 0 to 5.5 V
20
µA
µA
mA
pF
off
I
O
= 5.5 V,
= 5.5 V,
V = V
I
or GND,
I = 0
O
3
CC
CC
§
∆I
CC
Control inputs
One input at 3.4 V,
Other inputs at V
or GND
2.5
CC
C
C
Control inputs V = 3 V or 0
3.5
5.5
i
I
V
O
= 3 V or 0,
OE = V
pF
io(OFF)
CC
V
= 4 V,
CC
V = 2.4 V,
I
I = 15 mA
I
14
20
TYP at V
= 4 V
CC
¶
I = 64 mA
I
5
5
8
7
7
Ω
r
on
V = 0
I
V
CC
= 4.5 V
I = 30 mA
I
V = 2.4 V,
I
I = 15 mA
I
12
‡
§
¶
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL-voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
V
= 5 V
CC
± 0.5 V
V
= 4 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
MIN
MAX
0.25
4.9
†
t
t
t
A or B
OE
B or A
A or B
A or B
0.35
7.4
ns
ns
ns
pd
1.6
4.2
en
7.4
7.5
OE
dis
†
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
undershoot characteristics
‡
PARAMETER
TEST CONDITIONS
See Figures 1 and 2, and Table 1
= 5 V (unless otherwise noted), T = 25°C.
MIN
TYP
MAX
UNIT
V
2
V
–0.3
V
OUTU
OH
‡
All typical values are at V
CC
A
V
CC
V
TR
R1
50 Ω
DUT
R2
10 pF
5.5 V
V
IN
0 V
–2 V
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage Waveform
Table 1. Device Test Conditions
PARAMETER
VALUE
UNIT
§
B port under test
See Figure 1
V
See Figure 2
V
ns
ns
ns
kΩ
V
IN
t
w
20
2
t
r
t
2
f
R1 = R2
100
11
5.5
V
TR
V
CC
V
§
Other B-port outputs are open.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
TEST
S1
7 V
Open
S1
t
Open
7 V
pd
/t
500 Ω
From Output
Under Test
t
PLZ PZL
/t
GND
t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
V
+ 0.3 V
1.5 V
1.5 V
OL
V
(see Note B)
OL
OH
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
V
OH
V
OH
– 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 3. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
74CBTK16245DGGRE4
74CBTK16245DGGRG4
74CBTK16245DGVRE4
74CBTK16245DGVRG4
74CBTK16245DLRG4
SN74CBTK16245DGGR
SN74CBTK16245DGVR
SN74CBTK16245DL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
48
48
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
TVSOP
SSOP
DGG
DGV
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
SSOP
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBTK16245DLG4
SN74CBTK16245DLR
SSOP
DL
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74CBTK16245DGGR TSSOP
SN74CBTK16245DGVR TVSOP
DGG
DGV
DL
48
48
48
2000
2000
1000
330.0
330.0
330.0
24.4
24.4
32.4
8.6
6.8
15.8
10.1
16.2
1.8
1.6
3.1
12.0
12.0
16.0
24.0
24.0
32.0
Q1
Q1
Q1
SN74CBTK16245DLR
SSOP
11.35
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74CBTK16245DGGR
SN74CBTK16245DGVR
SN74CBTK16245DLR
TSSOP
TVSOP
SSOP
DGG
DGV
DL
48
48
48
2000
2000
1000
346.0
346.0
346.0
346.0
346.0
346.0
41.0
41.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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amplifier.ti.com
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interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
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www.ti.com/military
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Military
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power.ti.com
microcontroller.ti.com
www.ti-rfid.com
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Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
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www.ti.com/wireless
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