SN74CBTLV16210_08 [TI]
LOW-VOLTAGE 20-BIT FET BUS SWITCH; 低电压20位FET总线开关
| 型号： | SN74CBTLV16210_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-VOLTAGE 20-BIT FET BUS SWITCH |
| 文件： | 总11页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢋꢉ ꢌ
ꢇ ꢍ ꢎꢏꢈꢍ ꢇꢆꢐꢑ ꢒ ꢋ ꢌ ꢏꢅꢓ ꢆ ꢔ ꢒꢆ ꢅꢕꢀ ꢀ ꢎꢓ ꢆꢄ ꢖ
SCDS042J − DECEMBER 1997 − REVISED JULY 2004
DGV OR DL PACKAGE
(TOP VIEW)
D
Member of the Texas Instruments
Widebus Family
D
D
D
5-Ω Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
2A1
2A2
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2
I
Supports Partial-Power-Down Mode
3
off
Operation
4
5
description/ordering information
6
7
The SN74CBTLV16210 provides 20 bits of
high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
The device is organized as dual 10-bit bus
switches with separate output-enable (OE)
inputs. It can be used as two 10-bit bus switches
or as one 20-bit bus switch. When OE is low, the
associated 10-bit bus switch is on, and port A is
connected to port B. When OE is high, the switch
is open, and the high-impedance state exists
between the two ports.
V
CC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
This
device
is
fully
specified
for
partial-power-down applications using I . The I
off
off
feature ensures that damaging current will not
backflow through the device when it is powered
down. The device has isolation during power off.
To ensure the high-impedance state during power
NC − No internal connection
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74CBTLV16210DL
SN74CBTLV16210DLR
SN74CBTLV16210VR
SSOP − DL
CBTLV16210
CN210
−40°C to 85°C
Tape and reel
Tape and reel
TVSOP − DGV
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 10-bit bus switch)
INPUT
FUNCTION
OE
L
A port = B port
Disconnect
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢊ ꢋꢉ ꢌ
ꢇ ꢍꢎꢏꢈ ꢍꢇꢆꢐ ꢑꢒ ꢋ ꢌ ꢏꢅꢓ ꢆ ꢔꢒ ꢆ ꢅꢕ ꢀ ꢀ ꢎꢓ ꢆ ꢄꢖ
SCDS042J − DECEMBER 1997 − REVISED JULY 2004
logic diagram (positive logic)
2
46
36
1A1
1B1
SW
SW
12
48
13
1A10
1B10
1OE
2A1
35
25
2B1
SW
SW
24
47
2A10
2OE
2B10
simplified schematic, each FET switch
A
B
(OE)
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Package thermal impedance, θ (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢋꢉ ꢌ
ꢇ ꢍ ꢎꢏꢈꢍ ꢇꢆꢐꢑ ꢒ ꢋ ꢌ ꢏꢅꢓ ꢆ ꢔ ꢒꢆ ꢅꢕ ꢀ ꢀ ꢎꢓ ꢆꢄ ꢖ
SCDS042J − DECEMBER 1997 − REVISED JULY 2004
recommended operating conditions (see Note 3)
MIN
2.3
1.7
2
MAX
UNIT
V
V
Supply voltage
3.6
V
CC
V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
CC
CC
CC
CC
High-level control input voltage
V
IH
V
V
V
0.7
0.8
85
V
IL
Low-level control input voltage
Operating free-air temperature
V
T
A
−40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN TYP
MAX
−1.2
1
UNIT
V
V
V
V
V
V
V
= 3 V,
IK
CC
CC
CC
CC
CC
I
I
I
I
= 3.6 V,
= 0,
V = V
I CC
or GND
µA
µA
µA
µA
pF
I
V or V = 0 to 3.6 V
10
off
I
O
= 3.6 V,
= 3.6 V,
I
O
= 0,
V = V
I CC
or GND
10
CC
‡
∆I
CC
Control inputs
One input at 3 V,
Other inputs at V
CC
or GND
300
C
C
Control inputs V = 3 V or 0
4.5
6.5
5
i
I
V
O
= 3 V or 0,
OE = V
CC
pF
io(OFF)
I = 64 mA
8
8
I
V = 0
I
V
CC
= 2.3 V,
I = 24 mA
I
5
TYP at V
CC
= 2.5 V
V = 1.7 V,
I
I = 15 mA
I
27
40
§
on
Ω
r
I = 64 mA
5
5
7
7
I
V = 0
I
V
CC
= 3 V
I = 24 mA
I
V = 2.4 V,
I
I = 15 mA
I
10
15
†
‡
§
All typical values are at V
CC
= 3.3 V (unless otherwise noted), T = 25°C.
A
This is the increase in supply current for each input that is at the specified voltage level, rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CC
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
0.15
6.8
MIN
MAX
0.25
6
¶
t
t
t
A or B
OE
B or A
A or B
A or B
ns
ns
ns
pd
en
1
1
1
1
OE
7.3
7.4
dis
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢊ ꢋꢉ ꢌ
ꢇ ꢍꢎꢏꢈ ꢍꢇꢆꢐ ꢑꢒ ꢋ ꢌ ꢏꢅꢓ ꢆ ꢔꢒ ꢆ ꢅꢕ ꢀ ꢀ ꢎꢓ ꢆ ꢄꢖ
SCDS042J − DECEMBER 1997 − REVISED JULY 2004
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
Open
R
PLH PHL
L
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
GND
t
/t
PHZ PZH
C
L
R
L
(see Note A)
C
L
V
∆
R
V
CC
L
2.5 V 0.2 V
3.3 V 0.3 V
500 Ω
500 Ω
0.15 V
0.3 V
30 pF
50 pF
LOAD CIRCUIT
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
/2
Input
CC
0 V
V
0 V
t
t
t
PHL
t
t
PLH
PZL
PLZ
+ V
Output
Waveform 1
V
V
OH
CC
V
V
/2
/2
V
CC
/2
V
CC
/2
/2
Output
CC
S1 at 2 × V
(see Note B)
CC
V
OL
∆
V
OL
OL
t
t
t
PHL
PLH
/2
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2007
PACKAGING INFORMATION
Orderable Device
74CBTLV16210DLG4
74CBTLV16210DLRG4
74CBTLV16210GRG4
74CBTLV16210VRE4
74CBTLV16210VRG4
SN74CBTLV16210DL
SN74CBTLV16210DLR
SN74CBTLV16210GR
SN74CBTLV16210VR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DL
48
48
48
48
48
48
48
48
48
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
TSSOP
TVSOP
TVSOP
SSOP
DL
DGG
DGV
DGV
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
DGG
DGV
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74CBTLV16210DLR
SN74CBTLV16210GR
SN74CBTLV16210VR
SSOP
TSSOP
TVSOP
DL
48
48
48
1000
2000
2000
330.0
330.0
330.0
32.4
24.4
24.4
11.35
8.6
16.2
15.8
10.1
3.1
1.8
1.6
16.0
12.0
12.0
32.0
24.0
24.0
Q1
Q1
Q1
DGG
DGV
6.8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74CBTLV16210DLR
SN74CBTLV16210GR
SN74CBTLV16210VR
SSOP
TSSOP
TVSOP
DL
48
48
48
1000
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
49.0
41.0
41.0
DGG
DGV
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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