SN74CBTLV16211_08 [TI]
LOW-VOLTAGE 24-BIT FET BUS SWITCH;
| 型号： | SN74CBTLV16211_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-VOLTAGE 24-BIT FET BUS SWITCH |
| 文件： | 总6页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBTLV16211
LOW-VOLTAGE 24-BIT FET BUS SWITCH
SCDS043E – DECEMBER 1997 – REVISED APRIL 1999
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
5-Ω Switch Connection Between Two Ports
Isolation Under Power-Off Conditions
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
1A11
1A12
2A1
2A2
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B11
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B11
2B12
2
3
Latch-Up Performance Exceeds 250 mA Per
JESD 17
4
5
6
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
description
The SN74CBTLV16211 provides 24 bits of
high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
The device is organized as dual 12-bit bus
switches with separate output-enable (OE)
inputs. It can be used as two 12-bit bus switches
or one 24-bit bus switch. When OE is low, the
associated 12-bit bus switch is on and port A is
connected to port B. When OE is high, the switch
is open, and the high-impedance state exists
between the two ports.
V
CC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
To ensure the high-impedance state during power
up or power down, OE should be tied to V
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
2A10
2A11
2A12
CC
NC – No internal connection
The SN74CBTLV16211 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each 12-bit bus switch)
INPUT
FUNCTION
OE
L
A port = B port
Disconnect
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16211
LOW-VOLTAGE 24-BIT FET BUS SWITCH
SCDS043E – DECEMBER 1997 – REVISED APRIL 1999
logic diagram (positive logic)
2
54
42
1A1
1B1
SW
SW
14
1A12
1B12
56
1OE
15
41
29
2A1
2B1
SW
SW
28
2A12
2B12
55
2OE
simplified schematic, each FET switch
B
A
(OE)
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16211
LOW-VOLTAGE 24-BIT FET BUS SWITCH
SCDS043E – DECEMBER 1997 – REVISED APRIL 1999
recommended operating conditions (see Note 3)
MIN
2.3
1.7
2
MAX
UNIT
V
V
Supply voltage
3.6
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
High-level control input voltage
V
IH
0.7
0.8
85
V
IL
Low-level control input voltage
Operating free-air temperature
V
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
±1
UNIT
V
V
V
V
V
V
V
= 3 V,
IK
CC
CC
CC
CC
CC
I
I
I
I
= 3.6 V,
= 0,
V = V or GND
I CC
µA
µA
µA
µA
pF
I
V or V = 0 to 3.6 V
10
off
I
O
= 3.6 V,
= 3.6 V,
I
O
= 0,
V = V
I
or GND
10
CC
CC
‡
∆I
CC
Control inputs
One input at 3 V,
Other inputs at V
or GND
300
CC
C
C
Control inputs V = 3.3 V or 0
4.5
6.5
5
i
I
V
O
= 3.3 V or 0,
OE = V
CC
pF
io(OFF)
I = 64 mA
8
8
I
V = 0
I
V
= 2.3 V,
CC
I = 24 mA
I
5
TYP at V
= 2.5 V
CC
V = 1.7 V,
I
I = 15 mA
I
27
40
§
on
Ω
r
I = 64 mA
5
5
7
7
I
V = 0
I
V
CC
= 3 V
I = 24 mA
I
V = 2.4 V,
I
I = 15 mA
I
10
15
†
‡
§
All typical values are at V
This is the increase in supply current for each input that is at the specified voltage level rather than V
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
= 3.3 V (unless otherwise noted), T = 25°C.
A
CC
or GND.
CC
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
¶
t
t
t
A or B
OE
B or A
A or B
A or B
0.15
7
0.25
6.2
ns
ns
ns
pd
1
1
1
1
en
OE
7.2
7.7
dis
¶
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16211
LOW-VOLTAGE 24-BIT FET BUS SWITCH
SCDS043E – DECEMBER 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
TEST
S1
2 × V
CC
Open
GND
S1
t
Open
pd
/t
500 Ω
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
/t
t
PHZ PZH
C
= 30 pF
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
V
CC
V
CC
/2
V
CC
/2
LOAD CIRCUIT
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16211
LOW-VOLTAGE 24-BIT FET BUS SWITCH
SCDS043E – DECEMBER 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
6 V
TEST
S1
S1
500 Ω
Open
GND
From Output
Under Test
t
pd
/t
Open
6 V
t
PLZ PZL
C
= 50 pF
L
t
/t
GND
PHZ PZH
500 Ω
(see Note A)
Output
3 V
0 V
Control
(low-level
enabling)
1.5 V
1.5 V
LOAD CIRCUIT
t
PZL
t
PLZ
Output
Waveform 1
S1 at 6 V
3 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
OL
V
OL
(see Note B)
t
PHZ
t
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
– 0.3 V
0 V
1.5 V
Output
1.5 V
1.5 V
(see Note B)
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
C includes probe and jig capacitance.
L
ENABLE AND DISABLE TIMES
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1999, Texas Instruments Incorporated
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