SN74F161A [TI]
SYNCHRONOUS 4-BIT BINARY COUNTER; 同步4位二进制计数器
| 型号： | SN74F161A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS 4-BIT BINARY COUNTER |
| 文件： | 总9页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056A – D2932, MARCH 1987 – REVISED OCTOBER 1993
D OR N PACKAGE
(TOP VIEW)
• Internal Look-Ahead Circuitry for Fast
Counting
• Carry Output for N-Bit Cascading
• Fully Synchronous Operation for Counting
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
V
RCO
Q
CLR
CLK
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
A
Q
B
Q
B
C
D
C
Q
D
ENT
description
ENP
GND
LOAD
This synchronous, presettable, 4-bit binary
counter features an internal carry look-ahead
circuitry for application in high-speed counting
designs. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so
instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the
output counting spikes that are normally associated with asynchronous (ripple-clock) counters; however,
counting spikes may occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four
flip-flops on the rising (positive-going) edge of the clock input waveform.
This counter is fully programmable; that is, it may be preset to any number between 0 and 15. As presetting is
synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to
agree with the setup data after the next clock pulse regardless of the levels of the enable inputs.
The clear function for the SN74F161A is asynchronous and a low level at the clear (CLR) input sets all four of
the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable (ENP, ENT) inputs and a
ripple-carry (RCO) output. Both ENP and ENT must be high to count, and ENT if fed forward to enable RCO.
RCO thus enabled will produce a high-level pulse while the count is 15 (HHHH). The high-level overflow
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed
regardless of the level of the clock input.
The SN74F161A features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting
the setup and hold times.
The SN74F161A is characterized for operation from 0°C to 70°C.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056A – D2932, MARCH 1987 – REVISED OCTOBER 1993
†
logic symbol
state diagram
CTRDIV16
1
0
1
2
3
4
5
CT = 0
CLR
9
M1
M2
G3
LOAD
15
15
3CT = 15
RCO
10
ENT
7
2
ENP
CLK
G4
14
13
12
6
7
8
C5/2,3,4+
3
4
5
6
14
13
12
11
1
2
4
8
A
B
C
D
1, 5D
Q
A
Q
Q
B
C
11
10
9
Q
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056A – D2932, MARCH 1987 – REVISED OCTOBER 1993
logic diagram (positive logic)
1
CLR
9
LOAD
10
ENT
15
7
RCO
ENP
R
14
Q
A
G2
2
CLK
1, 2T/C3
3
A
1, 3D
M1
R
13
Q
G2
B
1, 2T/C3
4
B
1, 3D
M1
R
12
Q
G2
C
1, 2T/C3
5
C
1, 3D
M1
R
11
Q
G2
D
1, 2T/C3
6
1, 3D
M1
D
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056A – D2932, MARCH 1987 – REVISED OCTOBER 1993
logic symbol, each flip-flop
R
R
Q1
Q1
Q2
TE
G2
1, 2T/C3
CLK
D
1, 3D
M1
Q2
LOAD
logic diagram, each flip-flop (positive logic)
R
TE
(Toggle
Enable)
Q1
Q2
CLK
D
LOAD
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056A – D2932, MARCH 1987 – REVISED OCTOBER 1993
typical clear, preset, count, and inhibit sequences
Illustrated below is the following sequence:
1. Clear outputs to zero
2. Preset to binary twelve
3. Count to thirteen, fourteen, fifteen, zero, one, and two
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056A – D2932, MARCH 1987 – REVISED OCTOBER 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
–18
– 1
20
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
–1.2
V
IK
I
I
I
I
= – 1 mA
= – 1 mA
= 20 mA
2.5
2.7
3.4
0.3
OH
OH
OL
V
OH
OL
0.5
0.1
V
I
I
V = 7 V
I
mA
µA
I
IH
V = 2.7 V
I
20
ENP, CLK, A, B, C, D
ENT, LOAD
CLR
– 0.6
– 1.2
– 0.6
–150
55
I
V
= 5.5 V,
V = 0.5 V
mA
IL
CC
I
§
I
I
V
V
= 5.5 V,
= 5.5 V
V = 0
O
–60
mA
mA
OS
CC
CC
37
CC
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056A – D2932, MARCH 1987 – REVISED OCTOBER 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
Clock frequency
Pulse duration
100
0
5
90
MHz
clock
CLK high or low (loading)
CLK (counting)
5
High
Low
4
4
ns
ns
w
6
7
CLR low
5
5
Data before CLK↑
High or low
High
5
5
11
8.5
11
5
11.5
9.5
11.5
5
LOAD before CLK↑
t
su
Setup time
Low
High
ENP and ENT before CLK↑
Data after CLK↑
Low
High or low
High
2
2
2
2
t
t
Hold time
ns
ns
LOAD after CLK↑
h
Low
0
0
ENP and ENT after CLK↑
High or low
0
0
†
Inactive-state setup time, CLR high before CLK↑
6
6
su
†
Inactive-state state setup time is also referred to as recovery time.
switching characteristics (see Note 2)
V
C
R
= 5 V,
= 50 pF,
= 500 Ω,
= 25°C
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
CC
L
L
FROM
PARAMETER
TO
(OUTPUT)
= 500Ω,
= MIN to MAX
UNIT
(INPUT)
‡
T
A
T
A
MIN
100
2.7
2.7
3.2
3.2
4.2
4.2
1.7
1.7
4.7
3.7
TYP
120
5.1
7.1
5.6
5.6
9.6
9.6
4.1
4.1
8.6
7.6
MAX
MIN
90
MAX
f
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
t
t
t
t
t
t
t
t
7.5
10
2.7
2.7
3.2
3.2
4.2
4.2
1.7
1.7
4.7
3.7
8.5
11
CLK (LOAD high)
CLK (LOAD low)
CLK
Any Q
Any Q
RCO
8.5
8.5
14
9.5
9.5
15
ns
ns
ns
ns
14
15
7.5
7.5
12
8.5
8.5
13
ENT
CLR
RCO
Any Q
RCO
t
PHL
10.5
11.5
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuits and waveforms are shown in Section 1.
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–8
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明