SN74FB2041ARC [TI]
7-BIT TTL/BTL TRANSCEIVER; 7位TTL / BTL收发器
| 型号： | SN74FB2041ARC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 7-BIT TTL/BTL TRANSCEIVER |
| 文件： | 总9页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
Compatible With IEEE Std 1194.1-1991
(BTL)
High-Impedance State During Power Up
and Power Down
TTL A Port, Backplane Transceiver Logic
(BTL) B Port
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
Open-Collector B-Port Outputs Sink
100 mA
TTL Input Structures Incorporate Active
Clamping to Aid in Line Termination
Isolated Logic-Ground and Bus-Ground
Pins Reduce Noise
Packaged in Plastic Quad Flatpack
BIAS V
Pin Minimizes Signal Distortion
CC
During Live Insertion or Withdrawal
RC PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
2AI1
2AI2
2AO2
GND
2AO3
GND
2AI3
GND
2B1
GND
2B2
GND
2B3
GND
3B1
GND
3B2
GND
3B3
2
3
4
5
6
7
8
9
3AI1
10
11
12
13
3AO1
GND
3AO2
GND
GND
14 15 16 17 18 19 20 21 22 23 24 25 26
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
description
The SN74FB2041A device is a 7-bit transceiver designed to translate signals between TTL and backplane
transceiver logic (BTL) environments. It is specifically designed to be compatible with IEEE Std 1194.1-1991.
The B port operates at BTL signal levels. The open-collector B ports are specified to sink 100 mA. Two output
enables (OEB and OEB) are provided for the B outputs. When OEB is high and OEB is low, the B port is active
and reflects the inverse of the data present at the A-input pins. When OEB is low, OEB is high, or V
is less
CC
than 2.1 V, the B port is turned off. The enable/disable logic partitions the device as two 3-bit sections and one
1-bit section.
The A port operates at TTL signal levels and has split input and output pins. The A outputs reflect the inverse
of the data at the B port when the A-port output enable (OEA) is high. When OEA is low or when V
than 2.1 V, the A outputs are in the high-impedance state.
is less
CC
Pins are allocated for the four-wire IEEE Std 1149.1 (JTAG) test bus. TMS and TCK are not connected and TDI
is shorted to TDO.
BIAS V
establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when V
is not connected.
CC
CC
The SN74FB2041A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
FUNCTION
OEB
L
OEB
X
OEA
L
Isolation
X
H
L
L
X
H
B data to AO bus
X
H
H
H
L
L
AI data to B bus
H
L
H
AI data to B bus, B data to AO bus
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
†
logic symbol
46
47
OEB
G1
1OEA
EN2
45
20
1OEB
2OEA
1EN3
EN4
25
24
2OEB
3OEA
1EN5
EN6
26
1EN7
2
3OEB
40
50
51
52
2
1
1
1B1
1AO1
1AI1
3
5
38
4
2B1
2AO1
2AI1
36
4
2B2
2AO2
2AI2
3
6
34
2AO3
2B3
8
2AI3
10
32
3B1
6
1
3AO1
9
7
3AI1
3AO2
3AI2
30
12
14
3B2
28
16
18
3B3
3AO3
3AI3
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
functional block diagram
46
OEB
45
1OEB
47
1OEA
40
51
1B1
1AI1
50
1AO1
25
2OEB
20
2OEA
38
36
34
2
2B1
2B2
2AI1
52
2AO1
3
2AI2
4
2AO2
8
2B3
2AI3
6
2AO3
26
3OEB
24
3OEA
32
9
3B1
3AI1
10
3AO1
30
28
14
3B2
3B3
3AI2
12
3AO2
18
3AI3
16
3AO3
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V : Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V
Voltage range applied to any B output in the disabled or power-off state, V . . . . . . . . . . . . . . –0.5 V to 3.5 V
O
Voltage range applied to any output in the high state, V : A port . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
CC
Input clamp current, I : Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA
IK
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Current applied to any single output in the low state, I : A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 2)
MIN NOM
MAX
5.5
UNIT
V
CC,
BIAS V
,
Supply voltage
4.5
5
V
CC
BG V
CC
B port
1.62
2
2.3
V
High-level input voltage
Low-level input voltage
V
V
IH
IL
Except B port
B port
0.75
1.47
0.8
–18
–3
V
Except B port
I
I
Input clamp current
mA
mA
IK
High-level output current
AO port
AO port
B port
OH
OL
24
I
Low-level output current
mA
100
70
T
A
Operating free-air temperature
0
°C
NOTE 2: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
B port
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
–0.5
UNIT
V
V
= 4.5 V,
= 4.5 V,
CC
I
V
V
V
IK
Except B port
I = –40 mA
I
CC
I
I
I
I
I
I
= –1 mA
= –3 mA
= 20 mA
= 24 mA
= 80 mA
= 100 mA
OH
OH
OL
OL
OL
OL
AO port
V
V
V
= 4.5 V
= 4.5 V
= 4.5 V
V
V
OH
CC
CC
CC
2.5
3.3
AO port
B port
0.35
0.5
1.1
V
OL
0.75
1.15
50
I
I
Except B port
Except B port
Except B port
B port
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
V = 5.5 V
I
µA
µA
I
‡
= 5.5 V,
V = 2.7 V
I
50
IH
= 5.5 V,
V = 0.5 V
I
–50
–100
100
50
‡
µA
I
IL
= 5.5 V,
V = 0.75 V
I
I
I
I
I
I
I
B port
= 0 to 5.5 V,
= 5.5 V,
V
V
V
V
V
V
= 2.1 V
µA
µA
µA
µA
µA
mA
OH
O
O
O
O
O
O
AO port
= 2.7 V
OZH
OZL
AO port
= 5.5 V,
= 0.5 V
–50
50
AO port
= 0 to 2.1 V,
= 2.1 V to 0,
= 5.5 V,
= 0.5 V to 2.7 V
= 0.5 V to 2.7 V
= 0
OZPU
AO port
–50
–180
45
OZPD
§
AO port
–30
OS
AI port to B port
B port to AO port
AI port
I
V
CC
= 5.5 V,
I = 0
O
mA
CC
65
3
3
C
C
C
V = 0.5 V or 2.5 V
I
pF
pF
pF
i
Control inputs
AO port
V
V
V
= 0.5 V or 2.5 V
5.5
o
io
O
= 0 to 4.5 V
5
5
B port
CC
CC
per IEEE Std 1194.1-1991
= 4.5 V to 5.5 V
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
= 5 V, T = 25°C.
A
IH IL
CC
live-insertion specifications over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
= 0 to 2 V,
l
MIN
MAX
450
10
UNIT
µA
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0 to 4.5 V
= 4.5 V to 5.5 V
= 0,
I
(BIAS V
)
V
V (BIAS V ) = 4.5 V to 5.5 V
CC
CC
CC
B
V
B port
B port
V (BIAS V ) = 5 V
1.62
–1
2.1
V
O
I
CC
= 0,
V
B
= 1 V,
V (BIAS V ) = 4.5 V to 5.5 V
l CC
I
O
= 0 to 5.5 V,
= 0 to 2.2 V,
OEB = 0 to 0.8 V
OEB = 0 to 5 V
100
100
µA
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
2.3
2.6
2
TYP
3.9
4.1
3.6
3.8
4.6
4.7
4.3
4.2
3.2
2.8
2.4
3.8
0.5
0.4
1.6
1.4
MAX
5.1
5
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2
2.5
1.7
2
5.6
5.3
5.3
6.4
6.3
6.2
5.8
6.4
5.2
5
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(p)
sk(o)
AI
ns
ns
ns
ns
ns
ns
B
4.8
4.9
5.8
6
AO
B
2.3
3
2.6
3.1
2.6
2.5
1.5
1
OEB
B
3.1
2.7
2.7
1.5
1.1
1
5.6
5.3
5.2
5
OEB
OEA
B
AO
3.9
5.6
1
4.2
5.8
OEA
AO
2.2
1.7
†
†
Pulse skew, AI to B or B to AO
Pulse skew, AI to B or B to AO
Rise time, 1.3 V to 1.8 V, B outputs
Fall time, 1.8 V to 1.3 V, B outputs
B-port input pulse rejection
ns
ns
1
1
1
2.4
2.3
1
1
1
2.5
2.4
t
t
ns
ns
t
(pr)
†
Skew values are applicable for through mode only.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
2.1 V
16.5 Ω
7 V
Open
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
C
= 50 pF
C = 30 pF
L
(see Note A)
L
500 Ω
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
3 V
0 V
TEST
S1
Input
1.5 V
1.5 V
t
/t
Open
7 V
PLH PHL
/t
t
PLZ PZL
t
/t
Open
PHZ PZH
t
t
PLH
PHL
V
V
OH
3 V
0 V
Output
1.55 V
1.55 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A TO B)
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
2 V
1 V
V
V
+ 0.3 V
Input
1.55 V
1.55 V
OL
(see Note B)
V
OL
OH
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
V
V
OH
– 0.3 V
OH
Output
1.5 V
1.5 V
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B TO A)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES (A PORT)
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns,
O
r
t ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
f
O
r
f
Figure 1. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明