SN74GTLP22033GQLR [TI]
GTLP SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PBGA56, VFBGA-56;
| 型号： | SN74GTLP22033GQLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | GTLP SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PBGA56, VFBGA-56 输出元件 逻辑集成电路 触发器 |
| 文件： | 总19页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
DGG OR DGV PACKAGE
Member of the Texas Instruments
Widebus Family
(TOP VIEW)
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
IMODE1
AI1
IMODE0
BIAS V
B1
GND
OEAB
B2
ERC
OEAB
B3
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
CC
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
AO1
GND
AI2
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
AO2
V
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
CC
AI3
AO3
AO Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
GND 10
AI4
39 GND
CLKAB/LEAB
B4
11
12
38
37
AO4
LVTTL Interfaces Are 5-V Tolerant
AO5 13
AI5 14
36 B5
High-Drive GTLP Open-Drain Outputs
(100 mA)
35 CLKBA/LEBA
34 GND
GND 15
AO6 16
AI6 17
Reduced LVTTL Outputs (–12 mA/12 mA)
33 B6
32 OEBA
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
V
18
31
V
CC
CC
AO7 19
30 B7
AI7 20
29 LOOPBACK
28 GND
27 B8
GND 21
AO8 22
I
, Power-Up 3-State, and BIAS V
CC
off
Support Live Insertion
AI8 23
26
V
REF
25 OMODE1
Distributed V and GND Pins Minimize
CC
OMODE0 24
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLP22033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted
LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and
flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback
path for control and diagnostics monitoring, the same functionality as the SN74FB2033. The device provides
ahigh-speedinterfacebetweencardsoperatingatLVTTLlogiclevelsandabackplaneoperatingatGTLPsignal
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result
of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have
been designed and tested using several backplane models. The high drive allows incident-wave switching in
heavily loaded backplanes with equivalent load impedance down to 11 Ω.
The AO outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
description (continued)
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLP22033 is given only at the preferred higher noise margin GTLP, but the
user has the flexibility of using this device at either GTL (V = 1.2 V and V
= 0.8 V) or GTLP (V = 1.5 V
TT
REF
TT
and V
= 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
REF
application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and
GTLP in BTL Applications, literature number SCEA017.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and can be directly driven by TTL or 5-V CMOS devices. V
reference voltage.
is the B-port differential input
REF
This device is fully specified for live-insertion applications using I , power-up 3-state, and BIAS V . The I
off
off
CC
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
circuitry precharges and preconditions the B-port
CC
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between low and high adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, toensurethehigh-impedancestateabove1.5V,OEABshouldbetiedtoV throughapullupresistor
CC
and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the driver.
GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
IMODE1
AO1
2
3
4
5
NC
6
IMODE0
B1
A
B
C
D
E
F
NC
AI1
AI2
AI3
AI4
AI5
AI6
AI7
AI8
NC
NC
NC
A
B
C
D
E
F
GND
GND
ERC
GND
BIAS V
CC
AO2
V
OEAB
OEAB
B2
CC
AO3
GND
B3
AO4
CLKAB/LEAB
CLKBA/LEBA
OEBA
B4
AO5
B5
G
H
J
AO6
GND
GND
B6
G
H
J
AO7
V
V
LOOPBACK
B7
CC
CC
AO8
GND
NC
GND
NC
V
REF
NC
B8
K
OMODE0
OMODE1
K
NC = No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
TSSOP – DGG
TVSOP – DGV
Tape and reel
Tape and reel
SN74GTLP22033DGGR
SN74GTLP22033DGVR
GTLP22033
GT22033
–40°C to 85°C
VFBGA – GQL
Tape and reel
SN74GTLP22033GQLR
GS033
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
functional description
The SN74GTLP22033 is a high-drive (100 mA), 8-bit, three-wire registered transceiver containing D-type
latches and D-type flip-flops for data-path operation in the transparent, latched, or flip-flop modes. Data
transmission is complementary, with inverted AI data going to the B port and inverted B data going to AO. The
split LVTTL AI and AO provides a feedback path for control and diagnostics monitoring.
The logic element for data flow in each direction is configured by two mode (IMODE1 and IMODE0 for B to A,
OMODE1 and OMODE0 for A to B) inputs as a buffer, a D-type flip-flop, or a D-type latch. When configured in
the buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on the
rising edge of the appropriate clock (CLKAB/LEAB or CLKBA/LEBA) input. In the latch mode, the clock inputs
serve as active-high transparent latch enables.
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element (prior to inversion) is the B-to-A input.
The AO enable/disable control is provided by OEBA. When OEBA is low or when V
is in the high-impedance state. When OEBA is high, AO is active (high or low logic levels).
is less than 1.5 V, AO
CC
The B port is controlled by OEAB and OEAB. If OEAB is low, OEAB is high, or V
is inactive. If OEAB is high and OEAB is low, the B port is active.
is less than 1.5 V, the B port
CC
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO) or inactive (B port) states.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
Function Tables
FUNCTION/MODE
INPUTS
OUTPUT
MODE
OEBA OEAB OEAB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK
L
L
L
X
H
H
H
L
X
H
L
X
X
L
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
Z
Isolation
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Buffer
Flip-flop
Latch
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
Inverted AI to B
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
X
H
X
H
X
H
X
H
Inverted B to AO
Inverted B to AO
Inverted B to AO
AI to AO
Buffer
Flip-flop
Latch
X
L
L
L
L
L
H
H
X
X
L
L
X
L
L
L
H
H
L
L
X
L
L
H
H
H
H
H
H
Buffer
X
L
L
L
L
H
H
X
X
AI to AO
Flip-flop
Latch
X
L
L
H
H
AI to AO
X
Inverted AI to B,
Inverted B to AO
Transparent with
feedback path
H
H
L
X
X
X
X
L
ENABLE/DISABLE
INPUTS
OUTPUTS
OEBA
OEAB
OEAB
AO
B
L
H
X
X
X
X
X
X
L
X
X
L
Z
Active
Z
Z
L
H
L
H
H
Active
Z
H
BUFFER
INPUT
OUTPUT
L
H
L
H
LATCH
INPUTS
OUTPUT
CLK/LE DATA
H
H
L
L
H
X
H
L
Q
0
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
Function Tables (Continued)
LOOPBACK
†
Q
LOOPBACK
L
B port
‡
H
Point P
†
‡
Q is the input to the B-to-A
logic element.
P is the output of the A-to-B
logic element (see functional
block diagram).
SELECT
INPUTS
SELECTED
LOGIC ELEMENT
MODE1
MODE0
L
L
L
H
X
Buffer
Flip-flop
Latch
H
FLIP-FLOP
INPUTS
OUTPUT
CLK/LE DATA
L
↑
↑
X
L
Q
0
H
H
L
B-PORT EDGE-RATE CONTROL (ERC)
INPUT
ERC
OUTPUT
B-PORT
EDGE RATE
LOGIC LEVEL
H
L
Slow
Fast
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
functional block diagram
26
V
REF
42
44
ERC
OEAB
OEAB
41
24
25
38
OMODE0
OMODE1
CLKAB/LEAB
Transceiver
1D
C1
46
B1
2
P
AI1
1D
C1
48
IMODE0
1
IMODE1
35
CLKBA/LEBA
1D
C1
3
AO1
Q
1D
32
C1
OEBA
One of Eight Channels
29
LOOPBACK
Pin numbers shown are for the DGG and DGV packages.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and BIAS V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
CC
Input voltage range, V (see Note 1): AI port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
B port and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
REF
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1): AO port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, I : AO port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Current into any A-port output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
IK
I
Output clamp current, I
OK
O
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
recommended operating conditions (see Notes 4 through 7)
MIN
NOM
MAX
UNIT
V
,
CC
BIAS V
Supply voltage
3.15
3.3
3.45
V
CC
GTL
1.14
1.35
0.74
0.87
1.2
1.5
0.8
1
1.26
1.65
0.87
1.1
V
V
V
V
V
Termination voltage
V
V
V
V
V
TT
REF
I
GTLP
GTL
Reference voltage
Input voltage
GTLP
B port
V
TT
5.5
Except B port and V
B port
V
CC
REF
V
+0.05
REF
High-level input voltage
Low-level input voltage
IH
IL
Except B port
B port
2
V
–0.05
REF
Except B port
0.8
–18
–12
12
I
I
Input clamp current
mA
mA
IK
High-level output current
AO
OH
OL
AO
I
Low-level output current
mA
B port
100
10
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
ns/V
µs/V
°C
20
CC
T
A
Operating free-air temperature
–40
85
NOTES: 4. All unused control and B-port inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI
CC
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
= 3.3 V first, I/O second, and
CC
V
CC
=3.3Vlast,becausetheBIASV
prechargecircuitryisdisabledwhenanyV
pinisconnected.ThecontrolandV inputs
CC
CC
REF
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable but, generally, GND is connected first.
6.
7.
V
V
and R can be adjusted to accommodate backplane impedances if the dc recommended I
ratings are not exceeded.
can be adjusted to optimize noise margins, but normally is two-thirds V . TI-OPC circuitry is enabled in the A-to-B direction
TT
TT OL
REF
TT
and is activated when V > 0.7 V above V
minimize current drain.
. If operated in the A-to-B direction, V
should be set to within 0.6 V of V to
TT
TT
REF REF
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
= 3.15 V,
I = –18 mA
–1.2
V
IK
CC
I
= 3.15 V to 3.45 V,
I
I
I
I
I
I
I
I
I
= –100 µA
= –6 mA
= –12 mA
= 100 µA
= 6 mA
V
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
V
OH
AO
2.4
2
V
V
V
CC
V
CC
V
CC
= 3.15 V
= 3.15 V to 3.45 V,
= 3.15 V
0.2
0.55
0.8
AO
= 12 mA
= 10 mA
= 64 mA
= 100 mA
V
OL
0.2
B port
V
= 3.15 V
0.4
CC
CC
0.55
AI and
control inputs
‡
V
= 3.45 V,
= 3.45 V,
V = 0 or 5.5 V
I
±10
µA
µA
I
I
I
V
V
V
V
= 0 to 5.5 V
= 0 to 2.3 V
±10
±10
40
AO
CC
O
‡
OZ
= 3.45 V, V
within 0.6 V of V ,
TT
B port
CC
REF
O
Outputs high
Outputs low
Outputs disabled
– 0.6 V,
CC
V
= 3.45 V, I = 0,
CC
O
I
AO or B port
40
mA
V (A-port or control input) = V
or GND,
CC
I
CC
V (B port) = V or GND
I
TT
40
V
CC
= 3.45 V, One AI or control input at V
§
1.5
mA
pF
∆I
CC
Other AI or control inputs at V
or GND
CC
AI
3.5
3.5
5
4.5
5.5
6
C
V = 3.15 V or 0
I
i
Control inputs
AO
C
C
V
V
= 3.15 V or 0
= 1.5 V or 0
pF
pF
o
O
B port
8.5
10
io
O
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
For I/O ports, the parameter I
OZ
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
includes the input leakage current.
or GND.
CC
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
µA
I
I
I
V
CC
V
CC
V
CC
= 0,
V or V = 0 to 5.5 V
off
I
O
= 0 to 1.5 V,
= 1.5 V to 0,
V
= 0.5 V to 3 V,
OEBA = V
OEBA = V
±30
±30
µA
OZPU
OZPD
O
O
CC
CC
V
= 0.5 V to 3 V,
µA
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
µA
µA
µA
mA
µA
V
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0,
BIAS V
CC
= 0,
V or V = 0 to 1.5 V
I O
off
= 0 to 1.5 V, BIAS V
= 0, V = 0.5 V to 1.5 V, OEAB = 0 and OEAB = V
±30
±30
5
OZPU
OZPD
CC
O
CC
= 0, V = 0.5 V to 1.5 V, OEAB = 0 and OEAB = V
CC
= 1.5 V to 0, BIAS V
= 0 to 3.15 V
= 3.15 V to 3.45 V
= 0,
CC
O
I
CC
BIAS V
= 3.15 V to 3.45 V,
V
O
(B port) = 0 to 1.5 V
CC
(BIAS V
)
10
CC
V
O
BIAS V
BIAS V
= 3.3 V,
I
O
= 0
0.95
1.05
CC
I
O
= 0,
= 3.15 V to 3.45 V,
V
O
(B port) = 0.6 V
–1
µA
CC
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (unless otherwise noted)
TT
REF
MIN
MAX
UNIT
MHz
ns
f
t
Clock frequency
Pulse duration
175
clock
CLKAB/LEAB or CLKBA/LEBA
AI before CLKAB↑
AI before CLKBA↑
B before CLKBA↑
AI before LEAB↓
AI before LEBA↓
B before LEBA↓
AI after CLKAB↑
AI after CLKBA↑
B after CLKBA↑
2.8
1.1
1.4
1
w
t
su
Setup time
ns
1.6
2.1
2.2
0.3
0.2
0.6
0.3
0
t
h
Hold time
ns
AI after LEAB↓
AI after LEBA↓
B after LEBA↓
0
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (see Figure 1)
TT
REF
FROM
(INPUT)
TO
(OUTPUT)
†
‡
PARAMETER
EDGE RATE
MIN TYP
MAX UNIT
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
175
3
MHz
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
7.4
ns
AI
(buffer)
B
Slow
3
7.1
2
5.9
ns
AI
(buffer)
B
Fast
2
5.8
1
6.1
ns
B
AO
–
(buffer)
1
5.4
4.2
3.2
3.2
2.8
2
8.6
ns
LEAB
(latch mode)
B
B
Slow
Fast
–
7.7
7.6
ns
LEAB
(latch mode)
6.7
7.3
ns
LEAB
(latch mode)
AO
AO
1.8
1
6.6
6
ns
LEBA
(latch mode)
–
1
5.2
3.8
3.1
2.5
2.5
3.5
3
7.5
ns
7
OEAB
OEAB
B
B
Slow
Fast
Slow
Fast
–
6
ns
6
7.5
ns
OEAB
OEAB
OEBA
OEBA
B
7.2
2.5
2.5
1
6
ns
6
B
5.3
ns
AO
AO
1
4.2
1
5.5
ns
–
1
5.2
4.4
3.6
3.2
3.1
2
8.8
ns
CLKAB
(flip-flop mode)
B
B
Slow
Fast
–
8.1
7.2
ns
CLKAB
(flip-flop mode)
6.9
7.5
ns
7
CLKAB
(flip-flop mode)
AO
AO
1.8
1
6
ns
CLKBA
(flip-flop mode)
–
1
5.6
3.8
3.2
2.7
2.7
1
8.7
ns
OMODE
OMODE
IMODE
B
Slow
8.2
7.2
ns
B
Fast
7.2
6
ns
AO
–
1
5.1
†
‡
Slow (ERC = H) and Fast (ERC = L)
All typical values are at V = 3.3 V, T = 25°C.
CC
A
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (see Figure 1) (continued)
TT
REF
FROM
(INPUT)
TO
(OUTPUT)
†
‡
PARAMETER
EDGE RATE
MIN TYP
MAX UNIT
t
t
t
t
2.5
2
6.8
ns
PLH
PHL
PLH
PHL
LOOPBACK
AO
–
5.4
1
6
ns
AI
AO
–
(loopback high)
1
5.5
Slow
Fast
2.8
1.5
5.5
3
Rise time, B-port outputs (20% to 80%)
Rise time, AO (10% to 90%)
t
ns
ns
r
f
Slow
Fast
Fall time, B-port outputs (80% to 20%)
Fall time, AO (90% to 10%)
t
1.8
4.5
†
‡
Slow (ERC = H) and Fast (ERC = L)
All typical values are at V = 3.3 V, T = 25°C.
CC
A
skew characteristics over recommended ranges of supply voltage and operating free-air
§
temperature (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
†
‡
PARAMETER
EDGE RATE
MIN TYP
MAX
UNIT
¶
0.5
0.5
0.4
0.4
0.5
0.5
0.4
0.4
1.4
0.6
1.8
0.9
1
1
t
t
t
t
t
t
t
t
sk(LH)
sk(HL)
sk(LH)
sk(HL)
sk(LH)
sk(HL)
sk(LH)
sk(HL)
AI
B
B
B
B
B
B
Slow
ns
¶
¶
¶
¶
¶
¶
¶
0.9
0.9
1
AI
Fast
Slow
Fast
ns
ns
ns
CLKAB/LEAB
CLKAB/LEAB
AI
1
0.9
0.9
2
Slow
Fast
Slow
Fast
1.4
2.5
1.8
¶
ns
t
sk(t)
CLKAB/LEAB
†
‡
§
¶
Slow (ERC = L) and Fast (ERC = H)
All typical values are at V = 3.3 V, T = 25°C.
CC
Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
/t and t – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
A
t
sk(LH) sk(HL)
sk(t)
outputs with the same packaged device. The specifications are given for specific worst-case V
and temperature and apply to any outputs
].
CC
] or in opposite directions, both low to high and high to low [t
switching in the same direction either high to low [t
] or low to high [t
sk(HL) sk(LH)
sk(t)
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
12.5 Ω
From Output
6 V
Open
GND
S1
500 Ω
From Output
Under Test
TEST
/t
S1
Open
6 V
Test
Point
t
t
PLH PHL
Under Test
t
/t
C
= 50 pF
PLZ PZL
L
500 Ω
/t
GND
(see Note A)
C
= 30 pF
PHZ PZH
L
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
t
w
3 V
3 V
Timing
Input
1.5 V
1.5 V
1.5 V
Input
0 V
0 V
t
t
h
su
VOLTAGE WAVEFORMS
PULSE DURATION
V
OH
Data
Input
V
M
V
M
0 V
3 V
0 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(V = 1.5 V for A port and 1 V for B port)
M
t
t
PHL
PLH
(V
OH
= 3 V for A port and 1.5 V for B port)
V
V
OH
Output
1 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(AI to B port)
1 V
3 V
Output
Control
OL
1.5 V
1.5 V
0 V
3 V
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
1.5 V
0 V
1.5 V
1 V
1 V
V
OL
+ 0.3 V
Input
V
OL
OH
(see Note B)
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
V
OH
– 0.3 V
1.5 V
1.5 V
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to AO)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(AO)
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application is probably a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be closely approximated to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer to better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
1.5 V
Z
O
= 50 Ω
.25”
1”
1”
.25”
11 Ω
Conn.
Conn.
Conn.
Conn.
L
L
= 14 nH
From Output
Under Test
Test
Point
1”
1”
1”
1”
C
= 18 pF
Rcvr
Rcvr
Rcvr
L
Drvr
Slot 1
Slot 2
Slot 19
Slot 20
Figure 3. High-Drive RLC Network
Figure 2. High-Drive Test Backplane
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
†
‡
TYP
PARAMETER
EDGE RATE
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
4.7
5
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
AI
(buffer)
ns
B
B
B
B
B
B
B
B
Slow
3.7
4
AI
(buffer)
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fast
5.5
5.8
4.6
4.8
5.8
6
LEAB
(latch mode)
Slow
LEAB
(latch mode)
Fast
CLKAB
(flip-flop mode)
Slow
4.9
4.9
5.5
5.7
4.5
4.7
1.8
1.1
3.4
2.6
CLKAB
(flip-flop mode)
Fast
OMODE
Slow
OMODE
Fast
Slow
Fast
Slow
Fast
t
r
Rise time, B-port outputs (20% to 80%)
Fall time, B-port outputs (80% to 20%)
t
f
†
‡
Slow (ERC = H) and Fast (ERC = L)
All typical values are at V
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
CC
A
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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www.ti.com/broadband
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www.ti.com/military
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Logic
interface.ti.com
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power.ti.com
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www.ti.com/opticalnetwork
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microcontroller.ti.com
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www.ti.com/wireless
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