SN74HC126DE4 [TI]
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS; 具有三态输出翻两番总线缓冲器GATES
| 型号： | SN74HC126DE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| 文件： | 总19页 (文件大小：528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E – MARCH 1984 – REVISED JULY 2003
Wide Operating Voltage Range of 2 V to 6 V
Typical t = 11 ns
pd
High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive Up
To 15 LSTTL Loads
6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Low Power Consumption, 80-µA Max I
CC
SN54HC126 . . . FK PACKAGE
(TOP VIEW)
SN54HC126 . . . J OR W PACKAGE
SN74HC126 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1OE
1A
V
CC
13 4OE
1
2
3
4
5
6
7
14
3
2
1
20 19
18
4A
NC
4Y
1Y
NC
4
5
6
7
8
12
11
10
9
1Y
4A
17
16
2OE
2A
4Y
2OE
NC
3OE
3A
15 NC
14
9 10 11 12 13
2Y
3OE
2A
8
GND
3Y
NC – No internal connection
description/ordering information
These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup
resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC126N
SN74HC126N
SN74HC126D
SN74HC126DR
SN74HC126DT
SN74HC126NSR
SN74HC126DBR
SN74HC126PW
SN74HC126PWR
SN74HC126PWT
SNJ54HC126J
SNJ54HC126W
SNJ54HC126FK
HC126
–40°C to 85°C
SOP – NS
HC126
HC126
SSOP – DB
TSSOP – PW
HC126
CDIP – J
CFP – W
LCCC – FK
SNJ54HC126J
SNJ54HC126W
SNJ54HC126FK
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E – MARCH 1984 – REVISED JULY 2003
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
H
H
L
H
L
X
Z
logic diagram (positive logic)
1
10
1OE
3OE
3A
2
3
6
9
8
1A
1Y
2Y
3Y
4Y
4
13
12
2OE
4OE
4A
5
11
2A
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E – MARCH 1984 – REVISED JULY 2003
recommended operating conditions (see Note 3)
SN54HC126
MIN NOM
SN74HC126
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
∆t/∆v
Input transition rise/fall time
= 4.5 V
= 6 V
ns
T
A
Operating free-air temperature
–55
–40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC126
SN74HC126
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
V
V = V or V
IH
5.9
V
OH
OL
I
IL
IL
I
I
= –6 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –7.8 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
0.5
8
0.1
0.1
0.1
0.1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
0.1
0.1
V
I
IH
I
I
= 6 mA
4.5 V
6 V
0.4
0.33
0.33
1000
5
OL
= 7.8 mA
0.4
OL
I
I
I
V = V
I
or 0
6 V
1000
10
nA
µA
µA
pF
I
CC
CC
V
O
= V
or 0
6 V
0.01
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
160
10
80
C
2 V to 6 V
3
10
10
i
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E – MARCH 1984 – REVISED JULY 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
47
SN54HC126
SN74HC126
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
120
24
MIN
MAX
180
36
MIN
MAX
150
30
2 V
4.5 V
6 V
t
t
t
t
A
Y
Y
14
ns
pd
en
dis
t
11
20
31
26
2 V
57
120
24
180
36
150
30
OE
OE
4.5 V
6 V
16
ns
ns
ns
12
20
31
26
2 V
35
120
24
180
36
150
30
Y
4.5 V
6 V
17
15
20
31
26
2 V
28
60
90
75
Any
4.5 V
6 V
8
12
18
15
6
10
15
13
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
67
SN54HC126
SN74HC126
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
150
30
MIN
MAX
225
45
MIN
MAX
188
38
2 V
4.5 V
6 V
t
pd
t
en
t
t
A
Y
Y
19
ns
15
25
39
33
2 V
100
20
135
27
202
40
169
36
OE
4.5 V
6 V
ns
ns
17
23
36
30
2 V
45
210
42
315
63
265
53
Any
4.5 V
6 V
17
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per gate
No load
45
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E – MARCH 1984 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
S1
S2
t
t
Open
Closed
Closed
Open
PZH
Test
Point
t
t
1 kΩ
1 kΩ
en
R
L
From Output
Under Test
PZL
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
C
dis
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Input
50%
50%
0 V
t
t
PLH
PHL
90%
V
V
OH
In-Phase
Output
90%
50%
10%
50%
10%
OL
t
t
r
f
f
V
CC
t
t
PLH
PHL
90%
Output
Control
50%
50%
V
V
OH
90%
t
0 V
Out-of-Phase
Output
50%
10%
50%
10%
t
t
PLZ
PZL
OL
t
≈V
CC
r
Output
Waveform 1
(See Note B)
50%
50%
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
10%
V
OL
OH
t
t
PZH
PHZ
V
CC
V
Output
Waveform 2
(See Note B)
90%
t
90%
90%
Input
50%
10%
50%
10%
0 V
≈0 V
t
r
f
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
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Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CDIP
SOIC
Drawing
5962-86848012A
5962-8684801CA
SN54HC126J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
J
SN74HC126D
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC126DBLE
SN74HC126DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC126DBRE4
SN74HC126DE4
SN74HC126DG4
SN74HC126DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
DB
D
D
D
D
D
D
D
D
N
14
14
14
14
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC126DRE4
SN74HC126DRG4
SN74HC126DT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC126DTE4
SN74HC126DTG4
SN74HC126N
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC126N3
SN74HC126NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC126NSR
SN74HC126NSRE4
SN74HC126PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
14
14
14
14
14
14
14
14
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
LCCC
PW
PW
PW
PW
PW
PW
FK
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC126PWE4
SN74HC126PWR
SN74HC126PWRE4
SN74HC126PWT
SN74HC126PWTE4
SNJ54HC126FK
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1
TBD
POST-PLATE N / A for Pkg Type
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SNJ54HC126J
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
(mm)
16
SN74HC126DBR
SN74HC126DR
SN74HC126NSR
SN74HC126PWR
DB
D
14
14
14
14
MLA
MLA
MLA
MLA
8.2
6.5
8.2
7.0
6.6
9.0
2.5
2.1
2.5
1.6
12
8
16
16
16
12
Q1
Q1
Q1
Q1
16
NS
PW
16
10.5
5.6
12
8
12
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74HC126DBR
SN74HC126DR
SN74HC126NSR
SN74HC126PWR
DB
D
14
14
14
14
MLA
MLA
MLA
MLA
333.2
333.2
333.2
338.1
333.2
333.2
333.2
340.5
28.58
28.58
28.58
20.64
NS
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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