SN74HC163NSRG4 [TI]

HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, GREEN, PLASTIC, SOP-16;


型号：	SN74HC163NSRG4
厂家：	TEXAS INSTRUMENTS
描述：	HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, GREEN, PLASTIC, SOP-16 光电二极管输出元件逻辑集成电路触发器
文件：	总29页 (文件大小：1036K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ

ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

SN54HC163 . . . J OR W PACKAGE

SN74HC163 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 80-µA Max I

CLR

CLK

RCO

Typical t = 14 ns

4-mA Output Drive at 5 V

Low Input Current of 1 µA Max

Internal Look-Ahead for Fast Counting

Carry Output for n-Bit Cascading

Synchronous Counting

ENP

GND

ENT

LOAD

Synchronously Programmable

SN54HC163 . . . FK PACKAGE

(TOP VIEW)

description/ordering information

These synchronous, presettable counters feature

an internal carry look-ahead for application in

high-speed counting designs. The ’HC163

devices are 4-bit binary counters. Synchronous

operation is provided by having all flip-flops

clocked simultaneously so that the outputs

change coincident with each other when

instructed by the count-enable (ENP, ENT) inputs

and internal gating. This mode of operation

eliminates the output counting spikes normally

associated with synchronous (ripple-clock)

counters. A buffered clock (CLK) input triggers the

four flip-flops on the rising (positive-going) edge of

the clock waveform.

20 19

9 10 11 12 13

NC − No internal connection

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP − N

SOIC − D

Tube of 25

Tube of 40

Reel of 2500

Reel of 250

Reel of 2000

Tube of 90

Reel of 2000

Reel of 250

Tube of 25

Tube of 150

Tube of 55

SN74HC163N

SN74HC163D

SN74HC163DR

SN74HC163DT

SN74HC163NSR

SN74HC163DBR

SN74HC163PW

SN74HC163PWR

SN74HC163PWT

SNJ54HC163J

HC163

SOP − NS

HC163

−40°C to 85°C

SSOP − DB

TSSOP − PW

HC163

CDIP − J

CFP − W

LCCC − FK

SNJ54HC163J

SNJ54HC163W

SNJ54HC163FK

−55°C to 125°C

SNJ54HC163W

SNJ54HC163FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ꢕ

ꢐ

ꢑ

ꢦ

ꢖ

ꢡ

ꢝ

ꢒ

ꢅ

ꢟ

ꢎ

ꢠ

ꢪ

ꢍ

ꢚ

ꢑ

ꢘ

ꢛ

ꢁ

ꢙ

ꢖ

ꢓ

ꢎ

ꢓ

ꢗ

ꢘ

ꢢ

ꢡ

ꢙ

ꢚ

ꢠ

ꢛ

ꢜ

ꢝ

ꢘ

ꢞ

ꢗ

ꢣ

ꢚ

ꢛ

ꢘ

ꢚ

ꢗ

ꢟ

ꢣ

ꢟ

ꢠ

ꢡ

ꢛ

ꢢ

ꢘ

ꢞ

ꢝ

ꢜ

ꢟ

ꢘ

ꢚ

ꢙ

ꢣ

ꢡ

ꢤ

ꢟ

ꢥ

ꢗ

ꢠ

ꢝ

ꢟ

ꢞ

ꢗ

ꢞ

ꢫ

ꢚ

ꢛ

ꢘ

ꢡ

ꢦ

ꢝ

ꢘ

ꢦ

ꢞ

ꢢ

ꢟ

ꢢ

ꢧ

ꢑ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢍ ꢮꢋ ꢕꢐ ꢯ ꢋꢈꢰꢂ ꢈꢂꢉ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ

ꢛ

ꢚ

ꢠ

ꢞ

ꢚ

ꢛ

ꢜ

ꢞ

ꢚ

ꢟ

ꢣ

ꢗ

ꢙ

ꢗ

ꢠ

ꢢ

ꢛ

ꢞ

ꢨ

ꢞ

ꢢ

ꢛ

ꢚ

ꢙ

ꢎ

ꢢ

ꢩ

ꢝ

ꢍ

ꢘ

ꢜ

ꢢ

ꢟ

ꢞ

ꢝ

ꢘ

ꢦ

ꢛ

ꢦ

ꢝ

ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ

ꢛ

ꢝ

ꢘ

ꢞ

ꢫ

ꢧ

ꢕ

ꢛ

ꢚ

ꢦ

ꢞ

ꢗ

ꢚ

ꢠ

ꢢ

ꢟ

ꢗ

ꢘ

ꢬ

ꢦ

ꢚ

ꢢ

ꢚ

ꢞ

ꢘ

ꢢ

ꢠ

ꢢ

ꢟ

ꢝ

ꢛ

ꢗ

ꢥ

ꢗ

ꢘ

ꢠ

ꢥ

ꢡ

ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢑ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢉ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ

ꢞ

ꢣ

ꢛ

ꢚ

ꢠ

ꢢ

ꢟ

ꢗ

ꢘ

ꢬ

ꢦ

ꢚ

ꢢ

ꢟ

ꢘ

ꢚ

ꢞ

ꢘ

ꢢ

ꢠ

ꢢ

ꢟ

ꢝ

ꢛ

ꢗ

ꢥ

ꢫ

ꢗ

ꢘ

ꢠ

ꢥ

ꢡ

ꢦ

ꢢ

ꢞ

ꢢ

ꢟ

ꢗ

ꢘ

ꢬ

ꢚ

ꢙ

ꢝ

ꢥ

ꢣ

ꢝ

ꢛ

ꢝ

ꢜ

ꢢ

ꢞ

ꢢ

ꢛ

ꢟ

ꢧ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

description/ordering information (continued)

These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As

presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs

to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR) input sets all four of

the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.

This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum

count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear

the counter to 0000 (LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.

Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a

high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the

level of CLK.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that

modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of

the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ

ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

logic diagram (positive logic)

LOAD

ENT

RCO

†

ENP

†

CLK

CLR

1, 2T/1C3

†

For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown

on the logic diagram of the D/T flip-flops.

Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

logic symbol, each D/T flip-flop

LD (Load)

TE (Toggle Enable)

CK (Clock)

1, 2T/1C3

Q (Output)

D (Inverted Data)

R (Inverted Reset)

logic diagram, each D/T flip-flop (positive logic)

†

The origins of LD and CK are shown in the logic diagram of the overall device.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ

ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

typical clear, preset, count, and inhibit sequence

The following sequence is illustrated below:

1. Clear outputs to zero (synchronous)

2. Preset to binary 12

3. Count to 13, 14, 15, 0, 1, and 2

4. Inhibit

CLR

LOAD

Data

Inputs

CLK

ENP

ENT

Data

Outputs

RCO

Count

Inhibit

Sync Preset

Clear

Async

Clear

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Output clamp current, I

(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Continuous current through V

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HC163

MIN NOM

SN74HC163

MIN NOM

UNIT

MAX

Supply voltage

1.5

= 2 V

= 4.5 V

= 6 V

3.15

4.2

3.15

4.2

High-level input voltage

= 2 V

0.5

1.35

1.8

0.5

1.35

1.8

= 4.5 V

= 6 V

Low-level input voltage

Input voltage

Output voltage

= 2 V

1000

500

400

125

1000

500

400

‡

= 4.5 V

= 6 V

∆t/∆v

Input transition rise/fall time

Operating free-air temperature

−55

−40

°C

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

‡

If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced

grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V

IL IH

= 2 V does not damage the device; however, functionally,

the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ

ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

= 25°C

SN54HC163

SN74HC163

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN

1.9

4.4

5.9

3.7

5.2

MAX

MIN

1.9

MAX

2 V

4.5 V

6 V

1.9 1.998

4.4 4.499

5.9 5.999

4.4

= −20 µA

5.9

V = V or V

= −4 mA

4.5 V

6 V

3.98

5.48

4.3

5.8

3.84

5.34

= −5.2 mA

2 V

0.002

0.001

0.17

0.15

0.1

0.26

100

0.1

4.5 V

6 V

= 20 µA

0.1

V = V or V

= 4 mA

4.5 V

6 V

0.4

0.33

1000

= 5.2 mA

0.4

V = V

or 0

6 V

1000

160

µA

V = V

or 0,

= 0

6 V

2 V to 6 V

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

= 25°C

SN54HC163

SN74HC163

UNIT

MIN

MAX

MIN

MAX

4.2

MIN

MAX

2 V

4.5 V

6 V

Clock frequency

Pulse duration

MHz

clock

2 V

150

135

170

160

120

225

205

255

240

100

190

170

215

200

4.5 V

6 V

CLK high or low

A, B, C, or D

LOAD low

2 V

4.5 V

6 V

2 V

4.5 V

6 V

2 V

4.5 V

6 V

Setup time before CLK↑

ENP, ENT

2 V

4.5 V

6 V

CLR low

2 V

4.5 V

6 V

CLR inactive

2 V

Hold time, all synchronous inputs after CLK↑

4.5 V

6 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

switching characteristics over recommended operating free-air temperature range, C = 50 pF

(unless otherwise noted) (see Figure 1)

= 25°C

TYP

SN54HC163

SN74HC163

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

MAX

MIN

4.2

MAX

MIN

MAX

2 V

4.5 V

6 V

MHz

max

2 V

215

325

270

4.5 V

6 V

RCO

Any Q

RCO

Any

CLK

ENT

2 V

205

310

255

4.5 V

6 V

2 V

195

295

245

4.5 V

6 V

2 V

110

4.5 V

6 V

operating characteristics, T = 25°C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Power dissipation capacitance

No load

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ

ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

High-Level

50%

Pulse

From Output

Under Test

Test

Point

0 V

= 50 pF

Low-Level

Pulse

(see Note A)

50%

0 V

LOAD CIRCUIT

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

50%

0 V

PLH

PHL

90%

In-Phase

Output

Reference

Input

90%

50%

10%

50%

10%

0 V

PLH

PHL

90%

Data

Input

90%

Out-of-Phase

Output

50%

10%

50%

10%

50%

10%

50%

10%

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.

C includes probe and test-fixture capacitance.

C. For clock inputs, f

is measured when the input duty cycle is 50%.

max

D. The outputs are measured one at a time with one input transition per measurement.

E. and t are the same as t

PLH

PHL pd

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

APPLICATION INFORMATION

n-bit synchronous counters

This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit

counter. The ’HC163 devices count in binary. Virtually any count mode (modulo-N, N -to-N , N -to-maximum)

can be used with this fast look-ahead circuit.

The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25°C and

4.5-V V ). The reason for this is that there is a glitch that is produced on the second stage’s RCO and every

succeeding stage’s RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in

addition to the bipolar equivalents (LS, ALS, AS).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ

ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

APPLICATION INFORMATION

LSB

CTR

CLR

Clear (L)

CT=0

LOAD

RCO

3CT=MAX

ENT

Count (H)/

Disable (L)

ENP

CLK

C5/2,3,4+

Load (L)

[1]

[2]

[3]

[4]

1,5D

Count (H)/

Disable (L)

Clock

CTR

CLR

LOAD

ENT

CT=0

3CT=MAX

ENP

CLK

C5/2,3,4+

[1]

[2]

[3]

[4]

1,5D

CTR

CLR

LOAD

ENT

CT=0

3CT=MAX

ENP

CLK

C5/2,3,4+

[1]

[2]

[3]

[4]

1,5D

CTR

CLR

CT=0

LOAD

ENT

3CT=MAX

ENP

CLK

C5/2,3,4+

1,5D [1]

[2]

[3]

[4]

To More-Significant Stages

Figure 2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

APPLICATION INFORMATION

n-bit synchronous counters (continued)

The glitch on RCO is caused because the propagation delay of the rising edge of Q of the second stage is

shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, Q , Q , Q , and Q

(ENT × Q × Q × Q × Q ). The resulting glitch is about 7−12 ns in duration. Figure 3 shows the condition in

which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to

other stages. Q , Q , and Q of the first and second stage are at logic one, and Q of both stages are at logic

zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, Q and RCO of the

first stage go high. On the rising edge of the third clock pulse, Q and RCO of the first stage return to a low level,

and Q of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears

because of the race condition inside the chip.

CLK

ENT1

, Q , Q

B1 C1 D1

RCO1, ENT2

, Q , Q

B2 C2 D2

RCO2

Glitch (7−12 ns)

Figure 3

The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock

edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the

inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (t ). In other words,

= 1/(t CLK-to-RCO + t ). For example, at 25°C at 4.5-V V , the clock-to-RCO propagation delay is

max

pd g CC

43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the

cascaded counters can use is 18 MHz. The following tables contain the f

applications that use more than two ’HC163 devices cascaded together.

, t , and f

specifications for

clock

max

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ

ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ

SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003

APPLICATION INFORMATION

n-bit synchronous counters (continued)

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

= 25°C

SN54HC163

SN74HC163

UNIT

MIN

MAX

3.6

MIN

MAX

2.5

MIN

MAX

2.9

2 V

4.5 V

6 V

Clock frequency

MHz

clock

2 V

140

200

170

Pulse duration, CLK high or low

4.5 V

6 V

switching characteristics over recommended operating free-air temperature range, C = 50 pF

(unless otherwise noted) (see Note 4)

T = 25°C

SN54HC163

SN74HC163

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

3.6

MAX

MIN

2.5

MAX

MIN

2.9

MAX

2 V

4.5 V

6 V

MHz

max

NOTE 4: These limits apply only to applications that use more than two ’HC163 devices cascaded together.

If the ’HC163 devices are used as a single unit, or only two cascaded together, then the maximum clock

frequency that the devices can use is not limited because of the glitch. In these situations, the devices can be

operated at the maximum specifications.

A glitch can appear on RCO of a single ’HC163 device, depending on the relationship of ENT to CLK. Any

application that uses RCO to drive any input, except an ENT of another cascaded ’HC163 device, must take

this into consideration.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

86076012A

ACTIVE

LCCC

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

86076012A

SNJ54HC

163FK

8607601EA

8607601FA

ACTIVE

CDIP

CFP

TBD

A42

N / A for Pkg Type

-55 to 125

8607601EA

SNJ54HC163J

8607601FA

SNJ54HC163W

JM38510/66304BEA

M38510/66304BEA

CDIP

JM38510/

66304BEA

JM38510/

66304BEA

SN54HC163J

SN74HC163D

ACTIVE

CDIP

SOIC

A42

N / A for Pkg Type

-55 to 125

-40 to 85

SN54HC163J

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

HC163

SN74HC163DE4

SN74HC163DG4

SN74HC163DR

SN74HC163DRE4

SN74HC163DRG4

SN74HC163DT

ACTIVE

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 85

HC163

Green (RoHS

& no Sb/Br)

HC163

2500

250

Green (RoHS

& no Sb/Br)

HC163

Green (RoHS

& no Sb/Br)

HC163

Green (RoHS

& no Sb/Br)

HC163

Green (RoHS

& no Sb/Br)

HC163

SN74HC163DTE4

SN74HC163DTG4

SN74HC163N

Green (RoHS

& no Sb/Br)

HC163

Green (RoHS

& no Sb/Br)

HC163

Pb-Free

(RoHS)

SN74HC163N

SN74HC163NE4

Pb-Free

(RoHS)

N / A for Pkg Type

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

-55 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

SN74HC163NSR

SN74HC163NSRE4

SN74HC163NSRG4

SN74HC163PW

ACTIVE

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

POST-PLATE

Level-1-260C-UNLIM

N / A for Pkg Type

HC163

ACTIVE

2000

Green (RoHS

& no Sb/Br)

HC163

Green (RoHS

& no Sb/Br)

TSSOP

LCCC

Green (RoHS

& no Sb/Br)

SN74HC163PWE4

SN74HC163PWG4

SN74HC163PWR

SN74HC163PWRE4

SN74HC163PWRG4

SN74HC163PWT

SN74HC163PWTE4

SN74HC163PWTG4

SNJ54HC163FK

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TBD

86076012A

SNJ54HC

163FK

SNJ54HC163J

SNJ54HC163W

ACTIVE

CDIP

CFP

TBD

A42

N / A for Pkg Type

-55 to 125

8607601EA

SNJ54HC163J

8607601FA

SNJ54HC163W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC163, SN74HC163 :

Catalog: SN74HC163

•

Automotive: SN74HC163-Q1, SN74HC163-Q1

•

Military: SN54HC163

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

Military - QML certified for Military and Defense Applications

•

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74HC163DR

SN74HC163NSR

SN74HC163PWR

SN74HC163PWT

SOIC

2500

2000

250

330.0

16.4

12.4

6.5

8.2

6.9

10.3

10.5

5.6

2.1

2.5

1.6

8.0

12.0

8.0

16.0

12.0

TSSOP

5.6

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74HC163DR

SN74HC163NSR

SN74HC163PWR

SN74HC163PWT

SOIC

2500

2000

250

333.2

367.0

345.9

367.0

28.6

38.0

35.0

TSSOP

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74HC163NSRG4 [TI]

相关型号：

SN74HC163PW

SN74HC163PWG4

SN74HC163PWR

SN74HC163PWT

SN74HC163PWTE4

SN74HC163PWTG4

SN74HC164

SN74HC164D

SN74HC164DE4

SN74HC164DG4

SN74HC164DR

SN74HC164DRE4