SN74HC20DT 概述
DUAL 4-INPUT POSITIVE-NAND GATES 双路4输入正与非门 逻辑芯片 栅极
SN74HC20DT 规格参数
是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Obsolete | 零件包装代码: | SOIC |
包装说明: | SOP, SOP14,.25 | 针数: | 14 |
Reach Compliance Code: | unknown | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | Factory Lead Time: | 1 week |
风险等级: | 5.15 | 系列: | HC/UH |
JESD-30 代码: | R-PDSO-G14 | JESD-609代码: | e4 |
长度: | 8.65 mm | 负载电容(CL): | 50 pF |
逻辑集成电路类型: | NAND GATE | 最大I(ol): | 0.004 A |
湿度敏感等级: | 1 | 功能数量: | 2 |
输入次数: | 4 | 端子数量: | 14 |
最高工作温度: | 85 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | SOP |
封装等效代码: | SOP14,.25 | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE | 包装方法: | TAPE AND REEL |
峰值回流温度(摄氏度): | 260 | 电源: | 2/6 V |
Prop。Delay @ Nom-Sup: | 28 ns | 传播延迟(tpd): | 140 ns |
认证状态: | Not Qualified | 施密特触发器: | NO |
座面最大高度: | 1.75 mm | 子类别: | Gates |
最大供电电压 (Vsup): | 6 V | 最小供电电压 (Vsup): | 2 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | INDUSTRIAL |
端子面层: | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式: | GULL WING |
端子节距: | 1.27 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | 宽度: | 3.9 mm |
Base Number Matches: | 1 |
SN74HC20DT 数据手册
通过下载SN74HC20DT数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆꢇ
ꢊꢋꢌ ꢍ ꢃ ꢎꢏꢁ ꢐꢋꢑ ꢐꢒ ꢀꢏ ꢑ ꢏꢓꢔ ꢎꢁꢌꢁꢊ ꢕ ꢌꢑꢔ ꢀ
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
D
D
D
Typical t = 11 ns
pd
4-mA Output Drive at 5 V
Low Power Consumption, 20-µA Max I
Low Input Current of 1 µA Max
CC
SN54HC20 . . . FK PACKAGE
(TOP VIEW)
SN54HC20 . . . J OR W PACKAGE
SN74HC20 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
1A
1B
14
13
12
11
10
9
V
CC
3
2
1
20 19
18
2D
2C
NC
2B
2A
2Y
2C
NC
NC
NC
NC
1C
NC
1D
4
5
6
7
8
NC
1C
17
16
1D
15 NC
14
9 10 11 12 13
1Y
2B
8
GND
NC − No internal connection
description/ordering information
The ’HC20 devices contain two independent 4-input NAND gates. They perform the Boolean function
Y = A • B • C • D or Y = A + B + C + D in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC20N
SN74HC20N
SN74HC20D
SN74HC20DR
SN74HC20DT
SN74HC20NSR
SN74HC20DBR
SN74HC20PW
SN74HC20PWR
SN74HC20PWT
SNJ54HC20J
SNJ54HC20W
SNJ54HC20FK
HC20
SOP − NS
HC20
HC20
−40°C to 85°C
SSOP − DB
TSSOP − PW
HC20
CDIP − J
CFP − W
LCCC − FK
SNJ54HC20J
SNJ54HC20W
SNJ54HC20FK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢆ ꢇ
ꢊ ꢋꢌꢍ ꢃ ꢎꢏ ꢁꢐ ꢋꢑ ꢐ ꢒꢀ ꢏ ꢑꢏ ꢓ ꢔꢎ ꢁꢌꢁ ꢊ ꢕ ꢌꢑꢔ ꢀ
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
H
L
B
C
H
X
X
L
D
H
X
X
X
L
H
X
L
L
H
H
H
H
X
X
X
X
X
X
logic diagram (positive logic)
1
1A
9
10
12
13
2A
2B
2C
2D
2
1B
6
8
1Y
2Y
4
1C
5
1D
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆꢇ
ꢊꢋꢌ ꢍ ꢃ ꢎꢏꢁ ꢐꢋꢑ ꢐꢒ ꢀꢏ ꢑ ꢏꢓꢔ ꢎꢁꢌꢁꢊ ꢕ ꢌꢑꢔ ꢀ
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC20
MIN NOM
SN74HC20
UNIT
MAX
MIN NOM
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC20
SN74HC20
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
OH
V
OL
V = V or V
IH
V
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
2
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
0.33
0.33
1000
20
OL
= 5.2 mA
0.4
OL
I
I
V = V
I
or 0
6 V
1000
40
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
10
i
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢆ ꢇ
ꢊ ꢋꢌꢍ ꢃ ꢎꢏ ꢁꢐ ꢋꢑ ꢐ ꢒꢀ ꢏ ꢑꢏ ꢓ ꢔꢎ ꢁꢌꢁ ꢊ ꢕ ꢌꢑꢔ ꢀ
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
45
SN54HC20
MIN MAX
SN74HC20
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
110
22
2 V
4.5 V
6 V
165
33
140
28
24
95
19
16
14
t
A, B, C, or D
Y
Y
ns
pd
t
11
19
28
2 V
27
75
110
22
t
4.5 V
6 V
9
15
ns
7
13
19
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
25
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
From Output
Under Test
Test
Point
Input
50%
50%
0 V
C
= 50 pF
L
t
t
PLH
PHL
90%
(see Note A)
V
V
OH
In-Phase
Output
90%
t
50%
10%
50%
10%
LOAD CIRCUIT
OL
t
r
f
f
t
t
PLH
PHL
90%
V
CC
V
V
90%
t
90%
OH
Input
50%
10%
50%
10%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
0 V
OL
t
r
f
t
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
D. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CFP
Drawing
5962-8403901VCA
5962-8403901VDA
84039012A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
W
FK
J
14
14
20
14
14
14
14
14
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
LCCC
CDIP
CFP
POST-PLATE N / A for Pkg Type
8403901CA
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
8403901DA
W
J
JM38510/65003BCA
SN54HC20J
CDIP
CDIP
SOIC
A42 SNPB
A42 SNPB
J
SN74HC20D
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC20DBR
SN74HC20DBRE4
SN74HC20DE4
SN74HC20DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
DB
DB
D
14
14
14
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC20DRE4
SN74HC20DRG4
SN74HC20DT
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC20DTE4
SN74HC20N
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC20N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
SN74HC20NE4
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC20NSR
SN74HC20NSRE4
SN74HC20PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
14
14
14
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC20PWE4
SN74HC20PWG4
SN74HC20PWR
SN74HC20PWRE4
SN74HC20PWRG4
SN74HC20PWT
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74HC20PWTE4
ACTIVE
TSSOP
PW
14
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54HC20FK
SNJ54HC20J
SNJ54HC20W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74HC20DT 替代型号
型号 | 制造商 | 描述 | 替代类型 | 文档 |
SN74HC20D | TI | DUAL 4-INPUT POSITIVE-NAND GATES | 完全替代 | |
SN74HC20NSR | TI | DUAL 4-INPUT POSITIVE-NAND GATES | 完全替代 | |
SN74HC20DR | TI | DUAL 4-INPUT POSITIVE-NAND GATES | 类似代替 |
SN74HC20DT 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
SN74HC20DTE4 | TI | DUAL 4-INPUT POSITIVE-NAND GATES | 获取价格 | |
SN74HC20DTG4 | TI | HC/UH SERIES, DUAL 4-INPUT NAND GATE, PDSO14, GREEN, PLASTIC, SOIC-14 | 获取价格 | |
SN74HC20FN | TI | IC,LOGIC GATE,DUAL 4-INPUT NAND,HC-CMOS,LDCC,20PIN,PLASTIC | 获取价格 | |
SN74HC20FN3 | TI | IC IC,LOGIC GATE,DUAL 4-INPUT NAND,HC-CMOS,LDCC,20PIN,PLASTIC, Gate | 获取价格 | |
SN74HC20J | TI | IC,LOGIC GATE,DUAL 4-INPUT NAND,HC-CMOS,DIP,14PIN,CERAMIC | 获取价格 | |
SN74HC20N | TI | DUAL 4-INPUT POSITIVE-NAND GATES | 获取价格 | |
SN74HC20N-10 | TI | HC/UH SERIES, DUAL 4-INPUT NAND GATE, PDIP14 | 获取价格 | |
SN74HC20N1 | TI | IC,LOGIC GATE,DUAL 4-INPUT NAND,HC-CMOS,DIP,14PIN,PLASTIC | 获取价格 | |
SN74HC20N3 | TI | DUAL 4-INPUT POSITIVE-NAND GATES | 获取价格 | |
SN74HC20NE4 | TI | DUAL 4-INPUT POSITIVE-NAND GATES | 获取价格 |
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