SN74HC374DW-00 [TI]
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20;
| 型号： | SN74HC374DW-00 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总23页 (文件大小：1183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS141E − DECEMBER 1982 − REVISED AUGUST 2003
D
D
Wide Operating Voltage Range of 2 V to 6 V
D
D
D
D
Low Power Consumption, 80-µA Max I
Typical t = 14 ns
pd
6-mA Output Drive at 5 V
CC
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
D
Eight D-Type Flip-Flops in a Single Package
Full Parallel Access for Loading
Low Input Current of 1 µA Max
D
SN54HC374 . . . FK PACKAGE
(TOP VIEW)
SN54HC374 . . . J OR W PACKAGE
SN74HC374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
1
2
3
4
5
6
7
8
9
20
19
18
3
2
1
20 19
18
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
15 6Q
14
9 10 11 12 13
6D
GND 10
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ’HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 2000
Reel of 250
Tube of 20
Tube of 85
Tube of 55
SN74HC374N
SN74HC374N
SN74HC374DW
SN74HC374DWR
SN74HC374NSR
SN74HC374DBR
SN74HC374PWR
SN74HC374PWT
SNJ54HC374J
SOIC − DW
HC374
SOP − NS
HC374
HC374
−40°C to 85°C
−55°C to 125°C
SSOP − DB
TSSOP − PW
HC374
CDIP − J
CFP − W
LCCC − FK
SNJ54HC374J
SNJ54HC374W
SNJ54HC374FK
SNJ54HC374W
SNJ54HC374FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢉ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢒ ꢌꢐ ꢔꢑ ꢕ ꢐꢆꢯꢂ ꢆꢂꢈ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ
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ꢠ ꢟ ꢞ ꢙꢧ ꢞ ꢜꢧ ꢫ ꢞ ꢜꢜ ꢞ ꢙ ꢟꢬꢨ ꢔꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛꢙ ꢤꢜ ꢛꢡ ꢣꢠ ꢠꢘ ꢙꢭ ꢧꢛꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢃꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢃ
ꢉꢅ ꢊꢋ ꢌ ꢍꢎ ꢏꢍꢐꢊ ꢑꢒ ꢏꢏ ꢍꢑ ꢍꢎ ꢎꢐꢊ ꢓꢔ ꢍ ꢕꢌ ꢒꢔ ꢐꢕ ꢌꢉ ꢔꢀ
ꢖꢒ ꢊ ꢄ ꢆ ꢐꢀꢊꢋꢊ ꢍ ꢉꢗꢊ ꢔꢗ ꢊꢀ
SCLS141E − DECEMBER 1982 − REVISED AUGUST 2003
description/ordering information (continued)
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
2
1Q
3
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCLS141E − DECEMBER 1982 − REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC374
MIN NOM
SN74HC374
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC374
SN74HC374
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
V = V or V
IH
V
OH
OL
I
IL
IL
I
I
= −6 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −7.8 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
0.5
8
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V
V = V or V
V
I
IH
I
I
= 6 mA
4.5 V
6 V
0.4
0.33
0.33
1000
5
OL
= 7.8 mA
0.4
OL
I
I
I
V = V
I
or 0
6 V
1000
10
nA
µA
µA
pF
I
CC
V
O
= V
or 0
6 V
0.01
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
160
10
80
CC
C
2 V to 6 V
3
10
10
i
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉꢅ ꢊꢋ ꢌ ꢍꢎ ꢏꢍꢐꢊ ꢑꢒ ꢏꢏ ꢍꢑ ꢍꢎ ꢎꢐꢊ ꢓꢔ ꢍ ꢕꢌ ꢒꢔ ꢐꢕ ꢌꢉ ꢔꢀ
ꢖꢒ ꢊ ꢄ ꢆ ꢐꢀꢊꢋꢊ ꢍ ꢉꢗꢊ ꢔꢗ ꢊꢀ
SCLS141E − DECEMBER 1982 − REVISED AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC374
SN74HC374
A
V
UNIT
CC
MIN
MAX
6
MIN
MAX
4
MIN
MAX
5
2 V
4.5 V
6 V
30
20
24
f
t
t
t
Clock frequency
MHz
clock
35
24
28
2 V
80
16
14
100
20
17
10
5
120
24
20
150
30
25
13
5
100
20
17
125
25
21
12
5
4.5 V
6 V
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
ns
ns
ns
w
2 V
4.5 V
6 V
su
h
2 V
4.5 V
6 V
5
5
5
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
12
60
70
63
17
15
60
16
14
36
17
16
28
8
SN54HC374
SN74HC374
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4
MAX
MIN
5
MAX
2 V
4.5 V
6 V
30
35
20
24
24
28
f
t
t
t
t
MHz
max
pd
en
dis
t
2 V
180
36
270
54
225
45
4.5 V
6 V
CLK
OE
Any Q
Any Q
Any Q
Any Q
ns
ns
ns
ns
31
46
38
2 V
150
30
225
45
190
38
4.5 V
6 V
26
38
32
2 V
150
30
225
45
190
38
4.5 V
6 V
OE
26
38
32
2 V
60
90
75
4.5 V
6 V
12
18
15
6
10
15
13
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢃ
ꢀ
ꢀ
ꢖ ꢒꢊ ꢄ ꢆ ꢐꢀꢊꢋꢊ ꢍ ꢉ ꢗꢊ ꢔꢗ ꢊ
SCLS141E − DECEMBER 1982 − REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
12
SN54HC374
SN74HC374
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
MAX
MIN
5
MAX
2 V
4.5 V
6 V
30
35
60
24
28
f
t
t
t
MHz
max
pd
en
t
70
2 V
80
230
46
345
69
290
58
4.5 V
6 V
22
CLK
OE
Any Q
Any Q
Any Q
ns
ns
ns
19
39
58
49
2 V
70
200
40
300
60
250
50
4.5 V
6 V
25
22
34
51
43
2 V
45
210
42
315
63
265
53
4.5 V
6 V
17
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per flip-flop
No load
100
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢃꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢃ
ꢉꢅ ꢊꢋ ꢌ ꢍꢎ ꢏꢍꢐꢊ ꢑꢒ ꢏꢏ ꢍꢑ ꢍꢎ ꢎꢐꢊ ꢓꢔ ꢍ ꢕꢌ ꢒꢔ ꢐꢕ ꢌꢉ ꢔꢀ
ꢖꢒ ꢊ ꢄ ꢆ ꢐꢀꢊꢋꢊ ꢍ ꢉꢗꢊ ꢔꢗ ꢊꢀ
SCLS141E − DECEMBER 1982 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
PZH
S1
S2
Test
Point
t
t
1 kΩ
1 kΩ
en
t
t
t
R
PZL
PHZ
PLZ
L
From Output
Under Test
Open
Closed
Open
50 pF
C
dis
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
−−
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
High-Level
Pulse
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
90%
50%
10%
50%
10%
V
CC
Low-Level
Pulse
0 V
50%
50%
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
V
CC
V
CC
Control
(Low-Level
Enabling)
Input
50%
50%
50%
50%
0 V
V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
OH
≈V
CC
50%
≈V
CC
Output
Waveform 1
(See Note B)
In-Phase
Output
90%
t
50%
10%
50%
10%
10%
t
V
OL
V
OL
t
r
f
f
t
t
t
PZH
PHZ
PHL
90%
PLH
V
V
OH
V
Output
Waveform 2
(See Note B)
OH
90%
t
90%
Out-of-
Phase
Output
50%
10%
50%
10%
50%
≈0 V
OL
t
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
max
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-8407101VRA
ACTIVE
CDIP
CFP
J
20
20
20
1
TBD
TBD
TBD
A42
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
5962-8407101VR
A
SNV54HC374J
5962-8407101VSA
84071012A
ACTIVE
ACTIVE
W
1
1
-55 to 125
-55 to 125
5962-8407101VS
A
SNV54HC374W
LCCC
FK
POST-PLATE
84071012A
SNJ54HC
374FK
8407101RA
8407101SA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
J
20
20
20
20
1
1
1
1
TBD
TBD
TBD
TBD
TBD
A42
Call TI
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
8407101RA
SNJ54HC374J
8407101SA
SNJ54HC374W
JM38510/65602BRA
M38510/65602BRA
CDIP
CDIP
JM38510/
65602BRA
J
A42
JM38510/
65602BRA
SN54HC374J
ACTIVE
ACTIVE
CDIP
J
20
20
1
A42
N / A for Pkg Type
-55 to 125
-40 to 85
SN54HC374J
SN74HC374DBR
SSOP
DB
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HC374
SN74HC374DBRE4
SN74HC374DBRG4
SN74HC374DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
DB
DB
20
20
20
20
20
20
20
2000
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
HC374
HC374
HC374
HC374
HC374
HC374
HC374
Green (RoHS
& no Sb/Br)
DW
DW
DW
DW
DW
Green (RoHS
& no Sb/Br)
SN74HC374DWE4
SN74HC374DWG4
SN74HC374DWR
SN74HC374DWRE4
25
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74HC374DWRG4
SN74HC374N
ACTIVE
SOIC
PDIP
DW
20
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
HC374
ACTIVE
N
20
Pb-Free
(RoHS)
N / A for Pkg Type
-40 to 85
SN74HC374N
SN74HC374N3
SN74HC374NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
20
20
TBD
Call TI
Call TI
-40 to 85
-40 to 85
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HC374N
HC374
SN74HC374NSR
ACTIVE
ACTIVE
SO
SO
NS
NS
20
20
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
SN74HC374NSRG4
Green (RoHS
& no Sb/Br)
HC374
SN74HC374PWLE
SN74HC374PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
250
250
250
1
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HC374
HC374
HC374
HC374
HC374
HC374
SN74HC374PWRE4
SN74HC374PWRG4
SN74HC374PWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
LCCC
PW
PW
PW
PW
PW
FK
20
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74HC374PWTE4
SN74HC374PWTG4
SNJ54HC374FK
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TBD
84071012A
SNJ54HC
374FK
SNJ54HC374J
SNJ54HC374W
ACTIVE
ACTIVE
CDIP
CFP
J
20
20
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
8407101RA
SNJ54HC374J
W
Call TI
8407101SA
SNJ54HC374W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC374, SN54HC374-SP, SN74HC374 :
Catalog: SN74HC374, SN54HC374
•
Military: SN54HC374
•
Space: SN54HC374-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC374DBR
SN74HC374DWR
SN74HC374NSR
SN74HC374PWR
SN74HC374PWT
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
2000
2000
2000
2000
250
330.0
330.0
330.0
330.0
330.0
16.4
24.4
24.4
16.4
16.4
8.2
10.8
8.2
7.5
13.3
13.0
7.1
2.5
2.7
2.5
1.6
1.6
12.0
12.0
12.0
8.0
16.0
24.0
24.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
SO
TSSOP
TSSOP
PW
PW
6.95
6.95
7.1
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC374DBR
SN74HC374DWR
SN74HC374NSR
SN74HC374PWR
SN74HC374PWT
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
2000
2000
2000
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
45.0
45.0
38.0
38.0
SO
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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