SN74HC594D-00 [TI]
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16;
| 型号： | SN74HC594D-00 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总18页 (文件大小：964K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
D
D
Wide Operating Voltage Range of 2 V to 6 V
D
D
Low Input Current of 1 µA Max
8-Bit Serial-In, Parallel-Out Shift Registers
With Storage
High-Current Outputs Can Drive Up To
15 LSTTL Loads
D
D
D
Low Power Consumption, 80-µA Max I
Typical t = 15 ns
pd
6-mA Output Drive at 5 V
D
D
Independent Direct Overriding Clears on
Shift and Storage Registers
CC
Independent Clocks for Both Shift and
Storage Registers
SN54HC594 . . . J OR W PACKAGE
SN74HC594 . . . D, DW, OR N PACKAGE
(TOP VIEW)
SN54HC594 . . . FK PACKAGE
(TOP VIEW)
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Q
3
2
1
20 19
18
C
D
A
SER
RCLR
NC
Q
4
5
6
7
8
D
Q
SER
Q
17
16
15
E
Q
RCLR
RCLK
SRCLK
SRCLR
E
NC
Q
F
RCLK
Q
F
Q
G
14 SRCLK
9 10 11 12 13
Q
G
Q
H
GND
Q
H′
NC − No internal connection
description/ordering information
The ’HC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and
storage registers. A serial (Q ) output is provided for cascading purposes.
H′
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks
are connected together, the shift register always is one count pulse ahead of the storage register.
The parallel (Q −Q ) outputs have high-current capability. Q is a standard output.
A
H
H′
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Tube of 40
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
SN74HC594N
SN74HC594N
SN74HC594D
SN74HC594DR
SN74HC594DT
SN74HC594DW
SN74HC594DWR
SNJ54HC594J
SNJ54HC594W
SNJ54HC594FK
HC594
−40°C to 85°C
−55°C to 125°C
SOIC − DW
HC594
CDIP − J
CFP − W
LCCC − FK
SNJ54HC594J
SNJ54HC594W
SNJ54HC594FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
ꢔ ꢁ ꢖꢐꢀꢀ ꢓ ꢍꢄ ꢐꢏꢒ ꢌꢀ ꢐ ꢁ ꢓꢍꢐꢗ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢕꢏ ꢓ ꢗ ꢔ ꢅꢍ ꢌꢓ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢃꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢂ ꢆ ꢃ
ꢉꢊ ꢋꢌ ꢍ ꢀꢄ ꢌ ꢎ ꢍ ꢏ ꢐꢑ ꢌꢀ ꢍꢐ ꢏꢀ
ꢒꢌ ꢍ ꢄ ꢓꢔ ꢍ ꢕꢔ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏꢀ
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
L
X
X
X
↓
X
X
X
H
X
X
X
X
X
↑
↓
X
L
Shift register state is not changed.
Storage register is cleared.
H
H
Shift register data is stored in the storage register.
Storage register state is not changed.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
logic diagram (positive logic)
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
R
3R
C3
14
SER
1D
C1
15
Q
Q
A
B
R
3S
2S
2R
R
3R
1
C2
C3
R
3S
2S
2R
C2
R
3R
2
Q
Q
C
D
C3
R
3S
2S
2R
C2
R
3R
3
C3
R
3S
2S
2R
C2
R
3R
4
Q
Q
Q
E
F
C3
R
3S
2S
2R
C2
R
3R
5
C3
R
3S
2S
2R
C2
R
3R
6
G
C3
R
3S
2S
2R
C2
R
3R
C3
3S
7
9
Q
Q
H
R
H′
Pin numbers shown are for the D, DW, J, N, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢃꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢂ ꢆ ꢃ
ꢉꢊ ꢋꢌ ꢍ ꢀꢄ ꢌ ꢎ ꢍ ꢏ ꢐꢑ ꢌꢀ ꢍꢐ ꢏꢀ
ꢒꢌ ꢍ ꢄ ꢓꢔ ꢍ ꢕꢔ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏꢀ
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H′
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
SN54HC594
MIN NOM
SN74HC594
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
= 4.5 V
= 6 V
t
t
Input transition (rise and fall) time
Operating free-air temperature
ns
T
A
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC594
SN74HC594
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
3.7
5.2
5.2
MAX
MIN
1.9
MAX
2 V
1.9 1.998
4.4 4.499
5.9 5.999
4.5 V
6 V
4.4
I
= −20 µA
OH
5.9
Q
, I
H′ OH
= −4 mA
3.98
4.3
4.3
3.84
3.84
5.34
5.34
V
OH
V = V or V
IH IL
V
I
4.5 V
6 V
Q −Q , I
= −6 mA
3.98
5.48
5.48
A
H
OH
Q
, I
H′ OH
= −5.2 mA
5.8
Q −Q , I
= −7.8 mA
5.8
A
H
OH
2 V
4.5 V
6 V
0.002
0.001
0.001
0.17
0.17
0.15
0.15
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
OL
0.1
0.1
0.1
Q
, I
H′ OL
= 4 mA
= 6 mA
= 5.2 mA
0.26
0.26
0.26
0.26
100
0.5
0.4
0.33
0.33
0.33
0.33
1000
5
V
V = V or V
V
OL
I
IH
IL
4.5 V
6 V
Q −Q , I
OL
0.4
A
H
Q
, I
H′ OL
0.4
Q −Q , I
OL
= 7.8 mA
0.4
A
H
I
I
I
V = V
or 0
6 V
6 V
6 V
1000
10
nA
µA
µA
I
I
CC
V
O
= V
or 0
0.01
OZ
CC
CC
V = V
or 0,
I
O
= 0
8
160
80
I
CC
2 V
to 6 V
C
3
10
10
10
pF
i
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ꢞ ꢙꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝꢜ ꢟꢞꢘ ꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ
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5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢃꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢂ ꢆ ꢃ
ꢉꢊ ꢋꢌ ꢍ ꢀꢄ ꢌ ꢎ ꢍ ꢏ ꢐꢑ ꢌꢀ ꢍꢐ ꢏꢀ
ꢒꢌ ꢍ ꢄ ꢓꢔ ꢍ ꢕꢔ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏꢀ
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC594
SN74HC594
A
V
UNIT
CC
MIN
MAX
5
MIN
MAX
3.3
17
MIN
MAX
4
2 V
4.5 V
6 V
25
20
f
Clock frequency
Pulse duration
MHz
clock
29
20
24
2 V
100
20
17
100
20
17
90
18
15
90
18
15
50
10
9
150
30
25
150
30
25
135
27
23
135
27
23
75
15
13
20
10
10
5
125
25
21
125
25
21
110
22
19
110
22
19
63
13
11
20
10
10
5
4.5 V
6 V
SRCLK or RCLK high or low
SRCLR or RCLR low
t
w
ns
2 V
4.5 V
6 V
2 V
4.5 V
6 V
SER before SRCLK↑
2 V
†
4.5 V
6 V
SRCLK↑ before RCLK↑
2 V
4.5 V
6 V
t
su
Setup time
SRCLR low before RCLK↑
ns
2 V
20
10
10
5
4.5 V
6 V
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before SRCLK↑
2 V
4.5 V
6 V
5
5
5
5
5
5
2 V
5
5
5
t
h
Hold time, SER after SRCLK↑
4.5 V
6 V
5
5
5
ns
5
5
5
†
This setup time ensures that the output register receives stable data from the shift-register outputs. The clocks may be tied together, in which
case the output register is one clock pulse behind the shift register.
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ꢟ
ꢞ
ꢜ ꢡ ꢛ ꢚ ꢮ ꢢ ꢧꢙ ꢣ ꢛ ꢡ ꢝꢥ ꢜꢡ ꢰ ꢡ ꢩ ꢝꢧ ꢠꢡ ꢢ ꢘꢪ ꢅ ꢙꢣ ꢦꢣ ꢞꢘ ꢡꢦ ꢚꢛ ꢘꢚ ꢞ ꢜꢣ ꢘꢣ ꢣꢢ ꢜ ꢝꢘ ꢙꢡꢦ
ꢘ
ꢛ
ꢚ
ꢢ
ꢘ
ꢙ
ꢡ
ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢰ
ꢡ
ꢝ
ꢦ
ꢛ
ꢧ
ꢡ
ꢞ
ꢚ
ꢥ
ꢚ
ꢞ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢛ
ꢣ
ꢦ
ꢡ
ꢜ
ꢡ
ꢛ
ꢚ
ꢮ
ꢢ
ꢮ
ꢝ
ꢣ
ꢩ
ꢛ
ꢪ
ꢍ
ꢡ
ꢫ
ꢣ
ꢛ
ꢌ
ꢢ
ꢛ
ꢘ
ꢦ
ꢟ
ꢠ
ꢡ
ꢢ
ꢞ ꢙ ꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟ ꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝ ꢜꢟꢞ ꢘꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ
ꢘ
ꢛ
ꢦ
ꢡ
ꢛ
ꢡ
ꢦ
ꢰ
ꢡꢛ
ꢘ
ꢙ
ꢡ
ꢦ
ꢚ
ꢮ
ꢙ
ꢘ
ꢘ
ꢝ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢃ
ꢇ
ꢀ
ꢁ
ꢈ
ꢉ ꢊꢋꢌ ꢍ ꢀꢄꢌ ꢎ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢃ
ꢀ
ꢀ
ꢒ ꢌꢍ ꢄ ꢓ ꢔꢍ ꢕꢔꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏ
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
8
SN54HC594
SN74HC594
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
5
MAX
MIN
3.3
17
MAX
MIN
4
MAX
2 V
4.5 V
6 V
25
29
35
40
50
20
15
50
20
15
50
20
15
50
20
15
38
8
20
24
f
MHz
max
pd
20
2 V
150
30
225
45
185
37
4.5 V
6 V
SRCLK
RCLK
Q
H′
25
38
31
t
ns
ns
ns
2 V
150
30
225
45
185
37
4.5 V
6 V
Q −Q
A
H
H
H
25
38
31
2 V
150
30
225
45
185
37
4.5 V
6 V
SRCLR
RCLR
Q
H′
25
38
31
t
PHL
2 V
125
25
185
37
155
31
4.5 V
6 V
Q −Q
A
21
31
26
2 V
75
110
22
95
4.5 V
6 V
15
19
Q
H′
6
13
19
16
t
t
2 V
38
8
60
90
75
Q −Q
A
4.5 V
6 V
12
18
15
6
10
15
13
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
90
SN54HC594
SN74HC594
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
4.5 V
6 V
23
t
t
t
RCLK
RCLR
Q −Q
A
ns
pd
PHL
t
H
H
H
19
34
51
43
2 V
90
200
40
300
60
250
50
4.5 V
6 V
23
Q −Q
A
ns
ns
19
34
51
43
2 V
45
210
42
315
63
265
53
Q −Q
A
4.5 V
6 V
17
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
395
pF
pd
ꢕ
ꢏ
ꢓ
ꢗ
ꢔ
ꢅ
ꢍ
ꢕ
ꢏ
ꢐ
ꢯ
ꢌ
ꢐ
ꢒ
ꢚ
ꢢ
ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢞ
ꢝ
ꢢ
ꢞ
ꢡ
ꢦ
ꢢ
ꢛ
ꢧ
ꢦ
ꢝ
ꢜ
ꢟ
ꢜꢡ ꢛ ꢚ ꢮꢢ ꢧꢙ ꢣ ꢛ ꢡ ꢝꢥ ꢜꢡ ꢰ ꢡ ꢩꢝ ꢧꢠꢡ ꢢꢘꢪ ꢅ ꢙꢣ ꢦꢣ ꢞꢘ ꢡꢦ ꢚꢛ ꢘꢚ ꢞ ꢜꢣ ꢘꢣ ꢣꢢ ꢜ ꢝꢘ ꢙꢡꢦ
ꢞ
ꢘ
ꢛ
ꢚ
ꢢ
ꢘ
ꢙ
ꢡ
ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢰ
ꢡ
ꢝ
ꢦ
ꢛ
ꢧ
ꢡ
ꢞ
ꢚ
ꢥ
ꢚ
ꢞ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢛ
ꢣ
ꢦ
ꢡ
ꢜ
ꢡ
ꢛ
ꢚ
ꢮ
ꢢ
ꢮ
ꢝ
ꢣ
ꢩ
ꢛ
ꢪ
ꢍ
ꢡ
ꢫ
ꢣ
ꢛ
ꢌ
ꢢ
ꢛ
ꢘ
ꢦ
ꢟ
ꢠ
ꢡ
ꢢ
ꢞ ꢙꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝꢜ ꢟꢞꢘ ꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ
ꢘ
ꢛ
ꢦ
ꢡ
ꢛ
ꢡ
ꢦ
ꢰ
ꢡꢛ
ꢘ
ꢙ
ꢡ
ꢦ
ꢚ
ꢮ
ꢙ
ꢘ
ꢘ
ꢝ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢃꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢂ ꢆ ꢃ
ꢉꢊ ꢋꢌ ꢍ ꢀꢄ ꢌ ꢎ ꢍ ꢏ ꢐꢑ ꢌꢀ ꢍꢐ ꢏꢀ
ꢒꢌ ꢍ ꢄ ꢓꢔ ꢍ ꢕꢔ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏꢀ
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
Pulse
50%
50%
50%
From Output
Under Test
Test
Point
0 V
t
w
C
L
V
CC
(see Note A)
Low-Level
Pulse
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
F. t and t are the same as t .
f
r
t
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74HC594D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC594DE4
SN74HC594DG4
SN74HC594DR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC594DRE4
SN74HC594DRG4
SN74HC594DT
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC594DTE4
SN74HC594DTG4
SN74HC594DW
SN74HC594DWE4
SN74HC594DWG4
SN74HC594DWR
SN74HC594DWRE4
SN74HC594DWRG4
SN74HC594N
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
DW
DW
N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC594NE4
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC594DR
SN74HC594DWR
SN74HC594DWRG4
SOIC
SOIC
SOIC
D
16
16
16
2500
2000
2000
330.0
330.0
330.0
16.4
16.4
16.4
6.5
10.3
2.1
2.7
2.7
8.0
16.0
16.0
16.0
Q1
Q1
Q1
DW
DW
10.75 10.7
10.75 10.7
12.0
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC594DR
SN74HC594DWR
SN74HC594DWRG4
SOIC
SOIC
SOIC
D
16
16
16
2500
2000
2000
333.2
366.0
367.0
345.9
364.0
367.0
28.6
50.0
38.0
DW
DW
Pack Materials-Page 2
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