SN74HCT138N [TI]
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS; 3线路至8线路解码器/多路解复用器
| 型号： | SN74HCT138N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS |
| 文件： | 总6页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HCT138, SN74HCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS171C – MARCH 1984 – REVISED MAY 1997
SN54HCT138 . . . J OR W PACKAGE
SN74HCT138 . . . D, N, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
A
B
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
Y0
Y1
Y2
Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
C
G2A
G2B
G1
Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
12 Y3
11
10
9
Y4
Y5
Y6
Y7
GND
SN54HCT138 . . . FK PACKAGE
(TOP VIEW)
description
The ’HCT138 are designed for high-performance
memory-decoding or data-routing applications
requiring very short propagation delay times. In
high-performance memory systems, these
decoders can minimize the effects of system
decoding. When employed with high-speed
memories utilizing a fast enable circuit, the delay
timesofthesedecodersandtheenabletimeofthe
memory are usually less than the typical access
time of the memory. This means that the effective
system delay introduced by the decoders is
negligible.
3
2
1
20 19
18
Y1
Y2
NC
C
G2A
NC
4
5
6
7
8
17
16
15 Y3
14
9 10 11 12 13
G2B
G1
Y4
NC – No internal connection
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low (G) and one active-high (G) enable inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.
The SN54HCT138 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HCT138 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT138, SN74HCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS171C – MARCH 1984 – REVISED MAY 1997
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE
SELECT
G1
X
G2A
H
X
X
L
G2B
X
H
X
L
C
X
X
X
L
B
X
X
X
L
A
X
X
X
L
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y3
H
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
X
L
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
L
L
H
H
H
H
L
L
H
H
†
logic symbols (alternatives)
BIN/OCT
1
DMUX
0
15
15
0
Y0
1
0
Y0
A
B
C
1
2
4
A
B
C
0
2
14
13
12
14
13
12
2
3
2
3
1
2
3
Y1
Y2
Y3
1
2
3
Y1
Y2
Y3
G
7
11
10
9
11
10
9
4
5
6
Y4
Y5
Y6
4
5
6
Y4
Y5
Y6
&
&
6
4
5
6
4
5
G1
G2A
G2B
G1
G2A
G2B
EN
7
7
7
Y7
7
Y7
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT138, SN74HCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS171C – MARCH 1984 – REVISED MAY 1997
logic diagram (positive logic)
15
Y0
1
A
14
Y1
2
B
13
Y2
3
12
Y3
C
11
Y4
10
Y5
6
G1
9
Y6
4
G2A
7
Y7
5
G2B
Pin numbers shown are for the D, J, N, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT138, SN74HCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS171C – MARCH 1984 – REVISED MAY 1997
recommended operating conditions
SN54HCT138
MIN NOM MAX
SN74HCT138
MIN NOM MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0
0.8
0
0.8
V
CC
0
V
V
0
V
V
V
CC
CC
Output voltage
0
0
V
O
CC
CC
t
Input transition (rise and fall) time
Operating free-air temperature
0
500
125
0
500
85
ns
°C
t
T
–55
–40
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT138 SN74HCT138
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –20 µA
= –4 mA
= 20 µA
= 4 mA
4.4 4.499
OH
OH
OL
OL
V
V
V = V or V
IH
4.5 V
4.5 V
OH
I
IL
IL
3.98
4.3
0.001
0.17
3.7
3.84
0.1
0.26
±100
8
0.1
0.4
0.1
0.33
V = V or V
V
OL
I
IH
I
I
V = V
I
or 0
5.5 V
5.5 V
±0.1
±1000
160
±1000
80
nA
I
CC
CC
V = V
I
or 0,
I
O
= 0
µA
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
†
5.5 V
1.4
3
2.4
10
3
2.9
mA
pF
∆I
CC
CC
4.5 V
to 5.5 V
C
10
10
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
CC
.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
23
SN54HCT138 SN74HCT138
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
ns
CC
MIN
MAX
36
MIN
MAX
54
MIN
MAX
45
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
A, B, or C
Enable
Any Y
Any Y
Y
17
32
49
34
t
pd
t
22
33
50
42
18
30
45
38
12
15
22
19
t
ns
11
14
20
17
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
85
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT138, SN74HCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS171C – MARCH 1984 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
From Output
Under Test
Test
Point
Input
1.3 V
1.3 V
C
= 50 pF
L
t
t
PLH
PHL
90%
(see Note A)
V
V
OH
In-Phase
Output
90%
t
1.3 V
10%
1.3 V
10%
LOAD CIRCUIT
OL
t
r
f
f
t
t
PLH
PHL
90%
3 V
0 V
V
V
OH
2.7 V
2.7 V
Input
1.3 V
0.3 V
1.3 V
0.3 V
90%
t
Out-of-Phase
Output
1.3 V
10%
1.3 V
10%
OL
t
t
t
r
f
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
D. and t are the same as t
t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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