SN74HCT32D-00 [TI]
HCT SERIES, QUAD 2-INPUT OR GATE, PDSO14;
| 型号： | SN74HCT32D-00 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HCT SERIES, QUAD 2-INPUT OR GATE, PDSO14 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总17页 (文件大小：973K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Typical t = 13 ns
pd
4-mA Output Drive at 5 V
Low Power Consumption, 20-µA Max I
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
CC
SN54HCT32 . . . J OR W PACKAGE
SN74HCT32 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54HCT32 . . . FK PACKAGE
(TOP VIEW)
1A
1B
V
CC
4B
4A
1
2
3
4
5
6
7
14
13
12
3
2
1
20 19
18
4A
NC
4Y
1Y
NC
2A
4
5
6
7
8
1Y
17
16
2A
11 4Y
10
9
2B
3B
3A
3Y
15 NC
14
9 10 11 12 13
NC
2B
2Y
3B
8
GND
NC – No internal connection
description/ordering information
The ’HCT32 devices contain four independent 2-input OR gates. They perform the Boolean function
Y
A • B or Y
A
B
in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HCT32N
SN74HCT32N
SN74HCT32D
SN74HCT32DR
SN74HCT32DT
SN74HCT32NSR
SN74HCT32DBR
SN74HCT32PW
SN74HCT32PWR
SN74HCT32PWT
SNJ54HCT32J
SNJ54HCT32W
SNJ54HCT32FK
HCT32
–40°C to 85°C
SOP – NS
HCT32
HT32
SSOP – DB
TSSOP – PW
HT32
CDIP – J
CFP – W
LCCC – FK
SNJ54HCT32J
SNJ54HCT32W
SNJ54HCT32FK
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
H
H
L
logic diagram (positive logic)
A
B
Y
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT32
MIN NOM
SN74HCT32
MIN NOM
UNIT
MAX
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0.8
0.8
V
CC
0
0
V
V
0
0
V
V
V
CC
CC
Output voltage
V
O
CC
CC
∆t/∆v
Input transition rise/fall time
Operating free-air temperature
500
125
500
85
ns
°C
T
A
–55
–40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT32
SN74HCT32
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –20 µA
= –4 mA
= 20 µA
= 4 mA
4.4 4.499
OH
OH
OL
OL
V
V = V or V
IH
4.5 V
4.5 V
OH
OL
I
IL
IL
3.98
4.3
0.001
0.17
0.1
3.7
3.84
0.1
0.26
100
2
0.1
0.4
0.1
0.33
1000
20
V
V = V or V
V
I
IH
I
I
V = V
I
or 0
5.5 V
5.5 V
1000
40
nA
I
CC
CC
V = V
I
or 0,
I
O
= 0
µA
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
†
5.5 V
1.4
3
2.4
10
3
2.9
10
mA
pF
∆I
CC
CC
4.5 V
to 5.5 V
C
10
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
.
CC
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
15
SN54HCT32
SN74HCT32
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
ns
CC
MIN
MAX
24
MIN
MAX
35
MIN
MAX
30
4.5 V
5.5 V
4.5 V
5.5 V
t
t
A or B
Y
Y
pd
13
22
32
27
9
15
22
19
ns
t
8
14
20
17
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per gate
No load
20
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
From Output
Under Test
Test
Point
Input
1.3 V
1.3 V
C
= 50 pF
L
t
t
PLH
PHL
90%
(see Note A)
V
V
OH
In-Phase
Output
90%
t
1.3 V
10%
1.3 V
10%
LOAD CIRCUIT
OL
t
r
f
f
t
t
PLH
PHL
90%
3 V
0 V
V
V
OH
2.7 V
2.7 V
Input
1.3 V
0.3 V
1.3 V
0.3 V
90%
t
Out-of-Phase
Output
1.3 V
10%
1.3 V
10%
OL
t
t
t
r
f
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
D. and t are the same as t
t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN74HCT32D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32DBLE
SN74HCT32DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HT32
SN74HCT32DBRE4
SN74HCT32DBRG4
SN74HCT32DE4
SN74HCT32DG4
SN74HCT32DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DB
DB
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
HT32
Green (RoHS
& no Sb/Br)
HT32
Green (RoHS
& no Sb/Br)
HCT32
HCT32
HCT32
HCT32
HCT32
HCT32
HCT32
HCT32
SN74HCT32N
SN74HCT32N
HCT32
HCT32
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
250
250
250
25
Green (RoHS
& no Sb/Br)
SN74HCT32DRE4
SN74HCT32DRG4
SN74HCT32DT
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
SN74HCT32DTE4
SN74HCT32DTG4
SN74HCT32N
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Pb-Free
(RoHS)
SN74HCT32NE4
SN74HCT32NSR
SN74HCT32NSRE4
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
NS
NS
2000
2000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SO
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN74HCT32NSRG4
SN74HCT32PW
ACTIVE
SO
NS
14
14
14
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
HCT32
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
PW
PW
PW
90
90
90
Green (RoHS
& no Sb/Br)
-40 to 85
HT32
HT32
HT32
SN74HCT32PWE4
SN74HCT32PWG4
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
SN74HCT32PWLE
SN74HCT32PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HT32
HT32
HT32
HT32
HT32
HT32
SN74HCT32PWRE4
SN74HCT32PWRG4
SN74HCT32PWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74HCT32PWTE4
SN74HCT32PWTG4
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT32DBR
SN74HCT32DR
SN74HCT32DR
SN74HCT32DRG4
SN74HCT32DT
SN74HCT32NSR
SN74HCT32PWR
SN74HCT32PWT
SSOP
SOIC
SOIC
SOIC
SOIC
SO
DB
D
14
14
14
14
14
14
14
14
2000
2500
2500
2500
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
12.4
12.4
8.2
6.5
6.5
6.5
6.5
8.2
6.9
6.9
6.6
9.0
9.0
9.0
9.0
10.5
5.6
5.6
2.5
2.1
2.1
2.1
2.1
2.5
1.6
1.6
12.0
8.0
8.0
8.0
8.0
12.0
8.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
D
D
NS
PW
PW
2000
2000
250
TSSOP
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCT32DBR
SN74HCT32DR
SN74HCT32DR
SN74HCT32DRG4
SN74HCT32DT
SN74HCT32NSR
SN74HCT32PWR
SN74HCT32PWT
SSOP
SOIC
SOIC
SOIC
SOIC
SO
DB
D
14
14
14
14
14
14
14
14
2000
2500
2500
2500
250
367.0
333.2
367.0
333.2
367.0
367.0
367.0
367.0
367.0
345.9
367.0
345.9
367.0
367.0
367.0
367.0
38.0
28.6
38.0
28.6
38.0
38.0
35.0
35.0
D
D
D
NS
PW
PW
2000
2000
250
TSSOP
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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