SN74HCT541DW [TI]
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS; 八路缓冲器并用3态输出线路驱动器型号: | SN74HCT541DW |
厂家: | TEXAS INSTRUMENTS |
描述: | OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS |
文件: | 总6页 (文件大小:95K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54HCT541, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS306A – JANUARY 1996 – REVISED MAY 1997
SN54HCT541 . . . J OR W PACKAGE
SN74HCT541 . . . DW OR N PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive up
to 15 LSTTL Loads
OE1
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
OE2
Y1
1
2
3
4
5
6
7
8
9
20
19
18
Data Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
GND 10
These octal buffers and line drivers are designed
to have the performance of the popular ’HC240
series and to offer a pinout with inputs and outputs
on opposite sides of the package. This
arrangement greatly facilitates printed circuit
board layout.
SN54HCT541 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
Y1
Y2
Y3
A3
A4
A5
A6
A7
4
5
6
7
8
The 3-state control gate is a 2-input NOR. If either
output-enable (OE1 or OE2) input is high, all eight
outputs are in the high-impedance state. The
’HCT541 provide true data at the outputs.
17
16
15 Y4
14
9 10 11 12 13
Y5
The SN54HCT541 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HCT541 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OUTPUT
Y
OE1
L
OE2
L
A
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT541, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS306A – JANUARY 1996 – REVISED MAY 1997
†
logic symbol
1
&
OE1
19
EN
OE2
2
A1
3
18
17
16
15
14
13
12
11
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE1
OE2
19
2
18
A1
Y1
To Seven Other Channels
‡
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT541, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS306A – JANUARY 1996 – REVISED MAY 1997
recommended operating conditions
SN54HCT541
MIN NOM MAX
SN74HCT541
MIN NOM MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0
0.8
0
0.8
V
CC
0
V
V
0
V
V
V
CC
CC
Output voltage
0
0
V
O
CC
CC
t
Input transition (rise and fall) time
Operating free-air temperature
0
500
125
0
500
85
ns
°C
t
T
–55
–40
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT541 SN74HCT541
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –20 µA
= –6 mA
= 20 µA
= 6 mA
4.4 4.499
OH
OH
OL
OL
V
V
V = V or V
IH
4.5 V
4.5 V
OH
I
IL
IL
3.98
4.3
0.001
0.17
3.7
3.84
0.1
0.26
±100
±0.5
8
0.1
0.4
0.1
0.33
±1000
±5
V = V or V
V
OL
I
IH
I
I
I
V = V
I
or 0
5.5 V
5.5 V
5.5 V
±0.1
±1000
±10
nA
µA
µA
I
CC
V
O
= V
or 0,
V = V or V
±0.01
OZ
CC
CC
or 0,
I
IH
IL
V = V
I
I
O
= 0
160
80
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
†
5.5 V
1.4
3
2.4
10
3
2.9
mA
pF
∆I
CC
CC
4.5 V
to 5.5 V
C
10
10
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
CC
.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
13
SN54HCT541 SN74HCT541
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
ns
CC
MIN
MAX
23
MIN
MAX
34
MIN
MAX
29
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
t
t
t
t
A
Y
Y
Y
Y
pd
en
dis
t
12
21
31
26
21
30
45
38
ns
OE
OE
19
27
41
34
19
30
45
38
ns
18
27
41
34
8
12
18
15
ns
7
11
16
14
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT541, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS306A – JANUARY 1996 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
20
SN54HCT541 SN74HCT541
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
ns
CC
MIN
MAX
33
MIN
MAX
49
MIN
MAX
42
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
t
pd
t
en
t
t
A
Y
Y
Y
19
30
45
38
26
40
60
50
ns
OE
25
36
54
45
17
42
63
53
ns
14
38
57
48
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per buffer/driver
TEST CONDITIONS
TYP
UNIT
C
No load
35
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT541, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS306A – JANUARY 1996 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
S1
S2
L
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
S1
S2
PZH
Test
Point
t
t
1 kΩ
1 kΩ
en
R
t
L
PZL
From Output
Under Test
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
C
dis
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
Input
3 V
2.7 V
2.7 V
1.3 V
0.3 V
1.3 V
0.3 V
0 V
t
t
r
f
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3 V
0 V
Output
Control
(Low-Level
Enabling)
3 V
0 V
Input
1.3 V
1.3 V
1.3 V
1.3 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
V
OH
In-Phase
Output
≈ V
Output
Waveform 1
(See Note B)
CC
90%
t
1.3 V
10%
1.3 V
10%
1.3 V
10%
90%
OL
V
OL
t
r
f
f
t
t
t
PHL
90%
PLH
PZH
Out-of-
Phase
Output
V
V
OH
V
OH
Output
Waveform 2
(See Note B)
90%
t
1.3 V
10%
1.3 V
10%
1.3 V
OL
≈ 0 V
t
t
r
PHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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