SN74LS165ANE4 [TI]
PARALLEL-LOAD-8-BIT SHIFT REGISTERS; 并联负载8位移位寄存器
| 型号： | SN74LS165ANE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PARALLEL-LOAD-8-BIT SHIFT REGISTERS |
| 文件： | 总15页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
SN54165, SN54LS165A . . . J OR W PACKAGE
SN74165 . . . N PACKAGE
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
SN74LS165A . . . D, N, OR NS PACKAGE
(TOP VIEW)
Parallel-to-Serial Data Conversion
SH/LD
CLK
E
V
CC
CLK INH
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TYPICAL MAXIMUM
CLOCK FREQUENCY POWER DISSIPATION
TYPICAL
TYPE
’165
D
C
B
A
26 MHz
35 MHz
210 mW
90 mW
F
G
H
’LS165A
description
Q
SER
H
GND
Q
H
The ’165 and ’LS165A are 8-bit serial shift
registers that shift the data in the direction of Q
A
toward Q when clocked. Parallel-in access to
H
SN54LS165A . . . FK PACKAGE
(TOP VIEW)
each stage is made available by eight individual,
direct data inputs that are enabled by a low level
at the shift/load (SH/LD) input. These registers
also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All
inputs
are
diode-clamped
to minimize
3
2
1
20 19
18
transmission-line effects, thereby simplifying
system design.
4
5
6
7
8
D
C
NC
B
A
E
F
NC
G
17
16
15
14
Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD high enables the
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long asSH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD is low,
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.
H
9 10 11 12 13
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
Tube
Tube
SN74LS165AN
SN74LS165AD
SN74LS165ADR
SN74LS165ANSR
SN54LS165AJ
SN74LS165AN
0°C to 70°C
SOIC – D
SOP – NS
CDIP – J
CFP – W
LS165A
Tape and reel
Tape and reel
Tube
74LS165A
SN54LS165AJ
SNJ54LS165AJ
SNJ54LS165AW
SNJ54LS165AFK
Tube
SNJ54LS165AJ
SNJ54LS165AW
SNJ54LS165AFK
–55°C to 125°C
Tube
LCCC – FK Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INTERNAL
INPUTS
OUTPUTS
OUTPUT
Q
PARALLEL
A . . . H
H
CLK INH CLK
SER
SH/LD
Q
Q
B
A
L
X
L
X
L
↑
X
X
H
L
a . . . h
a
b
h
H
H
H
H
X
X
X
X
Q
Q
Q
Q
Q
Q
H0
Q
Gn
Q
Gn
Q
H0
A0
B0
An
An
B0
L
H
L
L
↑
H
X
X
Q
A0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
schematics of inputs and outputs
’165
EQUIVALENT OF EACH INPUT
TYPICAL OF BOTH OUTPUTS
V
CC
V
CC
100 Ω NOM
R
eq
Input
Output
SH/LD: R = 3 kΩ NOM
eq
Other Inputs: R = 6 kΩ NOM
eq
’LS165A
EQUIVALENT OF PARALLEL
INPUTS AND SERIAL INPUT
EQUIVALENT OF ALL
OTHER INPUTS
TYPICAL OF BOTH OUTPUTS
V
CC
V
CC
120 Ω NOM
R
eq
24 kΩ NOM
Input
Input
Output
CLK, CLK INH: R = 10 kΩ NOM
eq
SH/LD: R = 13 kΩ NOM
eq
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
logic diagram (positive logic)
A
B
C
D
E
F
G
H
11
12
13
14
3
4
5
F
6
1
SH/LD
15
CLK INH
2
CLK
SER
9
7
S
S
S
S
S
S
S
S
Q
Q
H
H
C1
C1
C1
C1
C1
C1
C1
C1
Q
Q
Q
Q
Q
Q
Q
G
10
A
B
C
D
E
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
Pin numbers shown are for D, J, N, NS, and W packages.
typical shift, load, and inhibit sequences
CLK
CLK INH
SER
L
SH/LD
A
H
L
B
C
H
L
D
E
F
Data
Inputs
H
L
H
H
G
H
L
L
L
Output Q
H
H
L
H
H
H
L
H
Output Q
L
L
L
H
H
H
H
Inhibit
Serial Shift
Load
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V : SN54165, SN74165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
SN54LS165A, SN74LS165A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Interemitter voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the ’165 to the SH/LD input in
conjunction with the CLK INH input.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54165
SN74165
UNIT
MIN NOM
MAX
5.5
MIN NOM
MAX
5.25
–800
16
V
CC
Supply voltage
4.5
5
4.75
5
V
A
I
I
f
t
t
t
t
t
t
t
High-level output current
–800
16
OH
Low-level output current
mA
MHz
ns
OL
Clock frequency
0
25
15
30
10
20
45
0
20
0
25
15
30
10
20
45
0
20
clock
w(clock)
w(load)
su
Width of clock input pulse
Width of load input pulse
ns
Clock-enable setup time (see Figure 1)
Parallel input setup time (see Figure 1)
Serial input setup time (see Figure 1)
Shift setup time (see Figure 1)
Hold time at any input
ns
ns
su
ns
su
ns
su
ns
h
T
A
Operating free-air temperature
–55
125
0
70
°C
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54165
SN74165
†
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
High-level input voltage
Low-level input voltage
Input clamp voltage
2
2
V
V
V
IH
0.8
0.8
IL
V
CC
= MIN, I = –12 mA
–1.5
–1.5
IK
I
V
V
= MIN,
= 0.8 V,
V
= 2 V,
= –800 A
CC
IL
IH
V
OH
V
OL
High-level output voltage
2.4
3.4
0.2
2.4
3.4
0.2
V
I
OH
V
V
= MIN,
= 0.8 V,
V
= 2 V,
= 16 mA
CC
IL
IH
Low-level output voltage
0.4
0.4
V
I
OL
I
Input current at maximum input voltage
V
= MAX, V = 5.5 V
1
80
1
80
mA
I
CC
I
SH/LD
High-level input current
Other inputs
I
V
= MAX, V = 2.4 V
µA
IH
IL
CC
CC
I
40
40
SH/LD
Low-level input current
Other inputs
–3.2
–1.6
–55
63
–3.2
–1.6
–55
63
I
V
= MAX, V = 0.4 V
I
mA
§
I
I
Short-circuit output current
Supply current
V
V
= MAX
–20
–18
mA
mA
OS
CC
= MAX, See Note 4
42
42
CC
CC
NOTE 4: With the outputs open, CLK INH and CLK at 4.5 V, and a clock pulse applied to SH/LD, I
at 4.5 V, then with the parallel inputs grounded.
is measured first with the parallel inputs
CC
†
‡
§
For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time.
CC
A
SN54165 and SN74165 switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
A
CC
FROM
(INPUT)
TO
(OUTPUT)
¶
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
t
t
t
t
t
t
20
26
21
27
16
21
11
24
MHz
max
PLH
PHL
PLH
PHL
PLH
PHL
31
40
24
31
17
36
Any
Any
C
C
C
C
= 15 pF, R = 400
ns
ns
ns
ns
LD
L
L
L
L
L
CLK
= 15 pF, R = 400
L
H
H
Q
Q
= 15 pF, R = 400
L
H
H
t
18
18
27
27
PLH
PHL
= 15 pF, R = 400
L
t
¶
f
= maximum clock frequency, t
PLH
= propagation delay time, low-to-high-level output, t = propagation delay time, high-to-low-level output
PHL
max
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
recommended operating conditions
SN54LS165A
MIN NOM MAX
SN74LS165A
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.7
–0.4
4
0.8
–0.4
8
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
0
15
25
25
17
30
10
20
45
0
25
0
15
25
25
17
30
10
20
45
0
25
Clock high
Clock low
Clock high
Clock low
t
Width of clock input pulse (see Figure 2)
Width of load input pulse
ns
ns
w(clock)
w(load)
t
t
su
t
su
t
su
t
su
t
h
Clock-enable setup time (see Figure 2)
Parallel input setup time (see Figure 2)
Serial input setup time (see Figure 2)
Shift setup time (see Figure 2)
Hold time at any input
ns
ns
ns
ns
ns
°C
T
A
Operating free-air temperature
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS165A
SN74LS165A
†
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= MIN,
= MIN,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
V
IH
= 2 V,
V
V
= MAX,
= MAX
I
I
I
= –0.4 mA
= 4 mA
2.5
3.5
2.7
3.5
0.25
0.35
OH
CC
IL
OH
OL
OL
0.25
0.4
0.4
0.5
V
OL
V
CC
= MIN,
V
IH
= 2 V,
V
IL
= 8 mA
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V = 7 V
0.1
20
0.1
mA
µA
I
I
= MAX, V = 2.7 V
20
IH
I
= MAX, V = 0.4 V
I
–0.4
–100
30
–0.4
–100
30
mA
mA
mA
IL
§
= MAX
–20
–20
OS
CC
= MAX, See Note 4
18
18
NOTE 4. With the outputs open, CLK INH and CLK at 4.5 V, and a clock pulse applied to SH/LD, I
at 4.5 V, then with the parallel inputs grounded.
is measured first with the parallel inputs
CC
†
‡
§
For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
CC
A
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
SN54LS165A and SN74LS165A switching characteristics, V
= 5 V, T = 25°C (see Figure 2)
A
CC
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
t
t
t
t
t
t
25
35
21
26
14
16
13
24
MHz
max
PLH
PHL
PLH
PHL
PLH
PHL
35
35
25
25
25
30
Any
Any
R
= 2 k , C = 15 pF
ns
ns
ns
ns
LD
L
L
L
L
L
CLK
R
R
R
= 2 k , C = 15 pF
L
H
H
Q
Q
= 2 k , C = 15 pF
L
H
H
t
19
17
30
25
PLH
PHL
= 2 k , C = 15 pF
L
t
†
f
= maximum clock frequency, t
PLH
= propagation delay time, low-to-high-level output, t = propagation delay time, high-to-low-level output
PHL
max
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
1 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.5 V
1.5 V
1.5 V
1.5 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
3 V
0 V
Input
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
1.5 V
V
OH
Output
(see Note D)
V
OL
+ 0.5 V
1.5 V
1.5 V
1.5 V
V
OL
V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
V
V
OH
1.5 V
1.5 V
≈1.5 V
(see Note D)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PZL
PLH PHL PHZ
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω; t and t ≤ 7 ns for Series
O
r
f
54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.
r
f
F. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
5 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
0 V
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
Output
(see Note D)
1.3 V
V
V
OH
V
OL
+ 0.5 V
1.3 V
1.3 V
1.3 V
V
OL
t
PHZ
OL
t
PZH
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
1.3 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PLH PHL PHZ
PZL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.
O
r
f
G. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CFP
Drawing
5962-7700601VEA
5962-7700601VFA
7700601EA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
J
W
J
16
16
16
16
20
16
16
16
16
16
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
CDIP
CFP
A42 SNPB
A42
7700601FA
W
FK
J
JM38510/30608B2A
JM38510/30608BEA
JM38510/30608BFA
SN54LS165AJ
LCCC
CDIP
CFP
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Call TI
W
J
CDIP
PDIP
SOIC
A42 SNPB
Call TI
SN74165N
N
D
SN74LS165AD
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS165ADE4
SN74LS165ADG4
SN74LS165ADR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS165ADRE4
SN74LS165ADRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS165AJ
SN74LS165AN
OBSOLETE
ACTIVE
CDIP
PDIP
J
16
16
TBD
Call TI
Call TI
N
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74LS165AN3
SN74LS165ANE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74LS165ANSR
ACTIVE
ACTIVE
SO
SO
NS
NS
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS165ANSRG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54LS165AFK
SNJ54LS165AJ
SNJ54LS165AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
SN74LS165ADR
SN74LS165ANSR
D
16
16
SITE 27
SITE 41
6.5
8.2
10.3
10.5
2.1
2.5
8
16
16
Q1
Q1
NS
330
16
12
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74LS165ADR
SN74LS165ANSR
D
16
16
SITE 27
SITE 41
342.9
346.0
336.6
346.0
28.58
33.0
NS
Pack Materials-Page 2
IMPORTANT NOTICE
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improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
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Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
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dsp.ti.com
www.ti.com/audio
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Digital Control
Military
www.ti.com/automotive
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www.ti.com/military
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interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
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Security
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Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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Copyright © 2007, Texas Instruments Incorporated
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