SN74LS16N [TI]
HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS; 六反相缓冲器/带集电极开路高压输出驱动程序
| 型号： | SN74LS16N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS |
| 文件： | 总13页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The SN74LS16 is obsolete
and is no longer supplied.
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SDLS020E − MAY 1990 − REVISED FEBRUARY 2004
SN54LS06 . . . J PACKAGE
SN74LS06, SN74LS16 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
D
D
D
D
D
Convert TTL Voltage Levels to MOS Levels
High Sink-Current Capability
Input Clamping Diodes Simplify System
Design
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1Y
2A
2Y
3A
V
CC
6A
6Y
5A
5Y
4A
4Y
Open-Collector Driver for Indicator Lamps
and Relays
Inputs Fully Compatible With Most TTL
Circuits
3Y
GND
8
description/ordering information
These hex inverter buffers/drivers feature
high-voltage open-collector outputs to interface
with high-level circuits (such as MOS), or for
driving high-current loads, and also are
characterized for use as inverter buffers for driving
TTL inputs. The ’LS06 devices have a rated output
voltage of 30 V, and the SN74LS16 has a rated
output voltage of 15 V. The maximum sink current
for the SN54LS06 is 30 mA, and for the
SN74LS06 and SN74LS16 it is 40 mA.
SN54LS06 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
6Y
NC
5A
NC
5Y
2A
NC
2Y
4
5
6
7
8
17
16
15
14
NC
3A
9 10 11 12 13
These devices are compatible with most TTL
families. Inputs are diode-clamped to minimize
transmission effects, which simplifies design.
Typical power dissipation is 175 mW, and average
propagation delay time is 8 ns.
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube
SN74LS06N
SN74LS06N
Tube
SN74LS06D
SOIC − D
SOP − NS
LS06
Tape and reel
Tape and reel
SN74LS06DR
SN74LS06NSR
SN74LS06DBR
SN54LS06J
0°C to 70°C
74LS06
SSOP − DB Tape and reel
LS06
Tube
CDIP − J
SN54LS06J
SNJ54LS06J
Tube
SNJ54LS06J
−55°C to 125°C
LCCC − FK
Tube
SNJ54LS06FK
SNJ54LS06FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
ꢗ ꢞ ꢩ ꢡ ꢠꢬ ꢧꢦ ꢤꢥ ꢦꢠ ꢢꢩ ꢫꢝ ꢣꢞ ꢤ ꢤꢠ ꢳꢍ ꢄꢙ ꢘꢏ ꢓ ꢙꢴꢵꢂ ꢴꢂꢇ ꢣꢫꢫ ꢩꢣ ꢡ ꢣ ꢢꢨ ꢤꢨꢡ ꢥ ꢣ ꢡ ꢨ ꢤꢨ ꢥꢤꢨ ꢬ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢀꢅ ꢆꢇ ꢀꢁ ꢈꢃ ꢄ ꢀꢅ ꢆ ꢇ ꢀ ꢁꢈ ꢃ ꢄꢀ ꢉ ꢆ
ꢊ ꢋꢌ ꢍ ꢁ ꢎꢋꢏ ꢐ ꢋꢏ ꢑꢒ ꢓꢓ ꢋꢏ ꢀꢔ ꢕ ꢏꢍ ꢎ ꢋꢏ ꢀ
The SN74LS16 is obsolete
and is no longer supplied.
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SDLS020E − MAY 1990 − REVISED FEBRUARY 2004
logic diagram (positive logic)
2
4
6
1
3
1Y
2Y
3Y
4Y
5Y
6Y
1A
2A
3A
4A
5A
6A
5
9
8
10
12
11
13
Pin numbers shown are for the D, DB, J, N, and NS packages.
schematic (each gate)
V
CC
2.5 kΩ
9 kΩ
1 kΩ
15 kΩ
Output
2.5 kΩ
Input
2 kΩ
2 kΩ
GND
Resistor values shown are nominal.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢊꢋꢌ ꢍꢁ ꢎꢋꢏ ꢐꢋ ꢏ ꢑꢒꢓ ꢓ ꢋꢏꢀ ꢔ ꢕꢏ ꢍ ꢎꢋ ꢏ
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The SN74LS16 is obsolete
and is no longer supplied.
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SDLS020E − MAY 1990 − REVISED FEBRUARY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Output voltage, V (see Notes 1 and 2): SN54LS06, SN74LS06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
O
SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. This is the maximum voltage that should be applied to any output when it is in the off state.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN74LS06
SN74LS16
SN54LS06
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.8
30
0.8
30
15
40
70
’LS06
V
OH
High-level output voltage
V
SN74LS16
I
Low-level output current
30
mA
OL
T
A
Operating free-air temperature
−55
125
0
°C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74LS06
SN54LS06
SN74LS16
‡
PARAMETER
UNIT
TEST CONDITIONS
I = −12 mA
§
§
MIN TYP
MAX
−1.5
0.25
MIN TYP
MAX
−1.5
0.25
0.25
0.4
V
IK
V
V
= MIN,
= MIN,
V
CC
I
’LS06,
V
OH
= 30 V
I
V
IL
= 0.8 V
mA
OH
CC
SN74LS16,
V
OH
= 15 V
I
I
I
= 16 mA
= 30 mA
= 40 mA
0.25
0.4
0.7
0.25
OL
OL
OL
V
OL
V
CC
= MIN,
V
IH
= 2 V
V
0.7
1
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX,
= MAX,
= MAX,
= MAX
= MAX
V = 7 V
I
1
20
mA
µA
I
V = 2.4 V
I
20
IH
V = 0.4 V
I
−0.2
18
−0.2
18
mA
mA
mA
IL
CCH
CCL
60
60
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, and T = 25°C.
CC
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢀꢅ ꢆꢇ ꢀꢁ ꢈꢃ ꢄ ꢀꢅ ꢆ ꢇ ꢀ ꢁꢈ ꢃ ꢄꢀ ꢉ ꢆ
ꢊ ꢋꢌ ꢍ ꢁ ꢎꢋꢏ ꢐ ꢋꢏ ꢑꢒ ꢓꢓ ꢋꢏ ꢀꢔ ꢕ ꢏꢍ ꢎ ꢋꢏ ꢀ
ꢖꢍ ꢐ ꢊ ꢗꢘꢋ ꢁꢙ ꢚꢗ ꢄꢄ ꢋꢚ ꢐꢗ ꢏ ꢊꢍ ꢛ ꢊꢙꢎ ꢗꢄꢐꢜꢛ ꢋ ꢗ ꢒꢐ ꢘꢒꢐ ꢀ
The SN74LS16 is obsolete
and is no longer supplied.
SDLS020E − MAY 1990 − REVISED FEBRUARY 2004
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
CC
A
FROM
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
MIN
MAX
UNIT
(INPUT)
t
t
7
15
20
PLH
A
R
= 110 Ω,
C
= 15 pF
L
ns
Y
L
10
PHL
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢊꢋꢌ ꢍꢁ ꢎꢋꢏ ꢐꢋ ꢏ ꢑꢒꢓ ꢓ ꢋꢏꢀ ꢔ ꢕꢏ ꢍ ꢎꢋ ꢏ
ꢇ
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ꢁ
ꢈ
ꢃ
ꢄ
ꢀ
ꢉ
ꢆ
ꢀ
ꢀ
The SN74LS16 is obsolete
and is no longer supplied.
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SDLS020E − MAY 1990 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
5 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
0 V
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
Output
(see Note D)
1.3 V
V
V
OH
V
OL
+ 0.5 V
1.3 V
1.3 V
1.3 V
V
OL
t
PHZ
OL
t
PZH
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
− 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
1.3 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
; S1 is closed and S2 is open for t .
PLH PHL PHZ
PLZ
PZH
PZL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.
O
r
f
G. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CDIP
SOIC
Drawing
5962-9861701Q2A
5962-9861701QCA
SN54LS06J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
14
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
1
SN74LS06D
D
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LS06DBLE
SN74LS06DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
None
Call TI
Call TI
2000
2500
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LS06DR
SN74LS06N
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
SO
D
N
14
14
14
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS06NSR
NS
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LS16D
SN74LS16DR
SN74LS16N
SNJ54LS06FK
SNJ54LS06J
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
PDIP
LCCC
CDIP
D
D
14
14
14
20
14
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
N
Call TI
FK
J
1
1
Level-NC-NC-NC
Level-NC-NC-NC
ACTIVE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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