SN74LV02ADG4_技术文档

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SCLS390J − APRIL 1998 − REVISED APRIL 2005

D

2-V to 5.5-V V

Operation

D

I

Supports Partial-Power-Down Mode

CC

off

Operation

Max t of 6.5 ns at 5 V

pd

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

CC

= 3.3 V, T = 25°C

A

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

Typical V

>2.3 V at V

(Output V

Undershoot)

OHV

CC

OH

= 3.3 V, T = 25°C

A

Support Mixed-Mode Voltage Operation on

All Ports

− 1000-V Charged-Device Model (C101)

SN54LV02A . . . J OR W PACKAGE

SN74LV02A . . . D, DB, DGV, NS,

OR PW PACKAGE

SN74LV02A . . . RGY PACKAGE

(TOP VIEW)

SN54LV02A . . . FK PACKAGE

(TOP VIEW)

3

2

1

20 19

18

1

14

1Y

1A

V

CC

1

2

3

4

5

6

7

14

13

12

11

4B

NC

4A

1B

NC

2Y

4

5

6

7

8

1A

1B

2Y

2A

2B

13 4Y

12 4B

2

3

4

5

6

4Y

4B

4A

17

16

1B

11

10

9

4A

3Y

3B

2Y

15 NC

NC

2A

10 3Y

14

9 10 11 12 13

3Y

9

8

2B

3B

3A

7

8

GND

NC − No internal connection

description/ordering information

The ’LV02A devices are quadruple 2-input positive-NOR gates designed for 2-V to 5.5-V V

operation.

CC

The ’LV02A devices perform the Boolean function Y = A + B or Y = A • B in positive logic.

These devices are fully specified for partial-power-down applications using I . The I circuitry disables the

off

outputs, preventing damaging current backflow through the devices when they are powered down.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

QFN − RGY

SOIC − D

Reel of 1000

Tube of 50

SN74LV02ARGYR

SN74LV02AD

LV02A

Reel of 2500

Reel of 2000

Tube of 90

SN74LV02ADR

SN74LV02ANSR

SN74LV02ADBR

SN74LV02APW

SN74LV02APWR

SN74LV02APWT

SN74LV02ADGVR

SNJ54LV02AJ

SOP − NS

74LV02A

LV02A

SSOP − DB

−40°C to 85°C

Reel of 2000

Reel of 250

Reel of 2000

Tube of 25

TSSOP − PW

LV02A

TVSOP − DGV

CDIP − J

LV02A

SNJ54LV02AJ

SNJ54LV102AW

SNJ54LV02AFK

−55°C to 125°C

CFP − W

Tube of 150

Tube of 55

SNJ54LV02AW

SNJ54LV02AFK

LCCC − FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2005, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢈ

ꢋꢌ ꢈ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢇ ꢑꢒ ꢁꢏ ꢌꢓ ꢏ ꢔꢀ ꢒ ꢓꢒ ꢅ ꢐꢑ ꢁꢔ ꢎ ꢕ ꢈꢓ ꢐꢀ

SCLS390J − APRIL 1998 − REVISED APRIL 2005

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

Y

A

B

X

H

L

H

X

L

H

logic diagram (positive logic)

A

Y

B

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Voltage range applied to any output in the high-impedance

or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

O

Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

CC

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA

IK

OK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

O

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Continuous current through V

O

CC

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

JA

(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W

(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W

(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W

(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 5.5 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

4. The package thermal impedance is calculated in accordance with JESD 51-5.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCLS390J − APRIL 1998 − REVISED APRIL 2005

recommended operating conditions (see Note 5)

SN54LV02A

SN74LV02A

UNIT

MIN

2

MAX

MIN

2

MAX

V

Supply voltage

5.5

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2 V

1.5

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

= 2 V

V

CC

V

CC

V

CC

× 0.7

V

CC

V

CC

V

CC

× 0.7

High-level input voltage

V

IH

0.5

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

V

× 0.3

5.5

V

× 0.3

CC

V

IL

Low-level input voltage

V

× 0.3

5.5

V

Input voltage

0

V

I

Output voltage

V

CC

O

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2 V

−50

−2

−50

−2

−6

−12

50

2

µA

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

= 2 V

I

High-level output current

Low-level output current

OH

OL

−6

mA

−12

50

µA

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

2

I

6

mA

12

200

100

20

85

200

100

20

∆t/∆v

Input transition rise or fall rate

Operating free-air temperature

ns/V

T

−55

125

−40

°C

A

NOTE 5: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LV02A

SN74LV02A

PARAMETER

TEST CONDITIONS

UNIT

V

CC

MIN

TYP

MAX

MIN

TYP

MAX

I

= −50 µA

= −2 mA

= −6 mA

= −12 mA

= 50 µA

= 2 mA

2 V to 5.5 V

2.3 V

V

CC

−0.1

2

V

CC

−0.1

2

OH

OL

V

OH

3 V

2.48

3.8

2.48

3.8

4.5 V

2 V to 5.5 V

2.3 V

0.1

0.4

0.44

0.55

1

0.1

0.4

0.44

0.55

1

V

OL

= 6 mA

3 V

= 12 mA

4.5 V

I

V = 5.5 V or GND

0 V to 5.5 V

5.5 V

µA

pF

I

V = V

CC

or GND,

I = 0

O

20

CC

off

I

V or V = 0 to 5.5 V

0

5

I

O

C

V = V

or GND

3.3 V

1.6

i

I

CC

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3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢈ

ꢋꢌ ꢈ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢇ ꢑꢒ ꢁꢏ ꢌꢓ ꢏ ꢔꢀ ꢒ ꢓꢒ ꢅ ꢐꢑ ꢁꢔ ꢎ ꢕ ꢈꢓ ꢐꢀ

SCLS390J − APRIL 1998 − REVISED APRIL 2005

switching characteristics over recommended operating free-air temperature range,

V

= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)

CC

T = 25°C

A

SN54LV02A

SN74LV02A

FROM

(INPUT)

TO

(OUTPUT)

LOAD

CAPACITANCE

PARAMETER

UNIT

MIN

TYP

MAX

MIN

1*

MAX

15*

19

MIN

1

MAX

15

C

= 15 pF

= 50 pF

8.3* 12.4*

11 16.1

L

t

pd

A or B

Y

ns

1

19

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating free-air temperature range,

V

= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)

CC

T

A

= 25°C

TYP

5.6*

SN54LV02A

SN74LV02A

FROM

(INPUT)

TO

(OUTPUT)

LOAD

CAPACITANCE

PARAMETER

UNIT

MIN

MAX

7.9*

MIN

1*

MAX

9.5*

13

MIN

1

MAX

9.5

C

= 15 pF

= 50 pF

L

t

pd

A or B

Y

ns

7.6

11.4

1

13

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating free-air temperature range,

V

= 5 V 0.5 V (unless otherwise noted) (see Figure 1)

CC

T

A

= 25°C

TYP

3.9*

SN54LV02A

SN74LV02A

FROM

(INPUT)

TO

(OUTPUT)

LOAD

CAPACITANCE

PARAMETER

UNIT

MIN

MAX

5.5*

7.5

MIN

1*

MAX

6.5*

8.5

MIN

1

MAX

6.5

C

= 15 pF

= 50 pF

L

t

pd

A or B

Y

ns

5.3

1

8.5

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

noise characteristics, V

= 3.3 V, C = 50 pF, T = 25°C (see Note 6)

CC

L

A

SN74LV02A

PARAMETER

UNIT

MIN

TYP

0.2

MAX

0.8

V

Quiet output, maximum dynamic V

V

OL(P)

OL(V)

OH(V)

IH(D)

IL(D)

OL

Quiet output, minimum dynamic V

High-level dynamic input voltage

Low-level dynamic input voltage

−0.1

3.2

−0.8

OL

OH

2.31

0.99

NOTE 6: Characteristics are for surface-mount packages only.

operating characteristics, T = 25°C

A

PARAMETER

TEST CONDITIONS

= 50 pF, f = 10 MHz

L

V

TYP

8.9

UNIT

CC

3.3 V

C

Power dissipation capacitance

C

pF

pd

5 V

10.3

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ꢞ ꢙ ꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟ ꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝ ꢜꢟꢞ ꢘꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ

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ꢘ

ꢝ

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ

ꢋ ꢌꢈꢍꢎ ꢌꢏꢄ ꢐ ꢇ ꢑꢒꢁ ꢏꢌꢓ ꢏꢔ ꢀꢒ ꢓ ꢒꢅꢐ ꢑꢁꢔꢎ ꢕ ꢈꢓꢐ ꢀ

SCLS390J − APRIL 1998 − REVISED APRIL 2005

PARAMETER MEASUREMENT INFORMATION

V

CC

Open

S1

R

= 1 kΩ

L

TEST

S1

From Output

Under Test

Test

Point

From Output

Under Test

GND

t

/t

Open

PLH PHL

/t

C

L

t

V

CC

L

PLZ PZL

/t

(see Note A)

GND

PHZ PZH

Open Drain

V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

3-STATE AND OPEN-DRAIN OUTPUTS

V

CC

50% V

CC

Timing Input

0 V

t

w

t

h

t

V

CC

su

V

CC

50% V

CC

50% V

CC

Input

50% V

CC

50% V

CC

Data Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

V

CC

Output

Control

50% V

CC

50% V

CC

50% V

t

CC

0 V

t

PZL

PLH

PHL

PLZ

Output

Waveform 1

V

OH

≈V

CC

In-Phase

Output

50% V

CC

50% V

CC

V

OL

+ 0.3 V

S1 at V

(see Note B)

CC

V

OL

t

PHL

PLH

PZH

PHZ

Output

Waveform 2

S1 at GND

V

OH

Out-of-Phase

Output

V

OH

− 0.3 V

50% V

CC

50% V

CC

≈0 V

V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. includes probe and jig capacitance.

C

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.

O

r

f

D. The outputs are measured one at a time, with one input transition per measurement.

E.

F.

G.

t

and t

PLH

are the same as t

.

dis

PLZ

PZL

PHL

PHZ

PZH

are the same as t

.

en

are the same as t .

pd

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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interface.ti.com

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power.ti.com

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www.ti.com/opticalnetwork

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www.ti.com/telephony

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Wireless

www.ti.com/video

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

26-May-2007

PACKAGING INFORMATION

Orderable Device

SN74LV02AD

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

14

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV02ADBR

SN74LV02ADBRE4

SSOP

DB

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV02ADBRG4

SN74LV02ADE4

ACTIVE

SSOP

SOIC

DB

D

14

2000

TBD

Call TI

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV02ADG4

SN74LV02ADGVR

SN74LV02ADGVRE4

SN74LV02ADGVRG4

SN74LV02ADR

ACTIVE

SOIC

TVSOP

SOIC

D

DGV

D

14

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV02ADRE4

SN74LV02ADRG4

SN74LV02ANSR

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

NS

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV02ANSRE4

SN74LV02APW

SO

NS

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

QFN

PW

RGY

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV02APWE4

SN74LV02APWG4

SN74LV02APWR

SN74LV02APWRE4

SN74LV02APWRG4

SN74LV02APWT

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV02APWTE4

SN74LV02APWTG4

SN74LV02ARGYR

SN74LV02ARGYRG4

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

26-May-2007

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

180

(mm)

16

SN74LV02ADBR

SN74LV02ADGVR

SN74LV02ADR

DB

DGV

D

14

MLA

8.2

6.8

6.5

8.2

7.0

3.85

6.6

4.0

2.5

1.6

2.1

2.5

1.6

1.35

12

8

16

12

Q1

12

16

9.0

8

SN74LV02ANSR

SN74LV02APWR

SN74LV02ARGYR

NS

16

10.5

5.6

12

8

PW

RGY

12

3.85

8

TAPE AND REEL BOX INFORMATION

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

SN74LV02ADBR

SN74LV02ADGVR

SN74LV02ADR

DB

DGV

D

14

MLA

342.9

338.1

342.9

338.1

190.0

336.6

340.5

336.6

340.5

212.7

28.58

20.64

28.58

20.64

31.75

SN74LV02ANSR

SN74LV02APWR

SN74LV02ARGYR

NS

PW

RGY

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

Pack Materials-Page 3

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

M

0,07

0,40

24

13

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

1

12

0,50

A

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

38

48

56

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153