SN74LV164AQWBQARQ1 [TI]
汽车级、八位、并行输出串行移位寄存器 | BQA | 14 | -40 to 125;
| 型号： | SN74LV164AQWBQARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、八位、并行输出串行移位寄存器 | BQA | 14 | -40 to 125 移位寄存器 |
| 文件： | 总22页 (文件大小：1549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV164A-Q1
ZHCSPK3 –DECEMBER 2022
SN74LV164A-Q1 汽车类8 位并行输出串行移位寄存器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
SN74LV164A-Q1 器件是 8 位并行输出串行移位寄存
器，可在2V 至5.5V VCC 下运行。
– 器件温度等级1：–40°C 至+125°C，TA
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C6
• 2V 至5.5V VCC 运行
• 5V 时tpd 最大值为10.5 ns
• VOLP（输出接地反弹）典型值
小于0.8V（VCC = 3.3V、TA = 25°C 时）
• VOHV（输出VOH 下冲）典型值
大于2.3V（VCC = 3.3V、TA = 25°C 时）
• Ioff 支持带电插入、局部关断模式以及后驱动保护
• 所有端口上均支持以混合模式
电压运行
器件信息(1)
封装尺寸（标称值）
器件型号
封装
BQA（WQFN，
14）
SN74LV164A-Q1
3.00mm x 2.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 闩锁性能超过250mA，符合
JESD 17 规范
2 应用
• 输出扩展
• LED 矩阵控制
• 7 段显示控制
8
CLK
1
A
D
R
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
Q
2
B
9
CLR
4
5
6
10
11
12
13
3
QA
QB
QC
QD
QE
QF
QG
QH
逻辑图（正逻辑）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS886
SN74LV164A-Q1
ZHCSPK3 –DECEMBER 2022
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Table of Contents
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................13
11 Layout...........................................................................14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 接收文档更新通知................................................... 15
12.2 支持资源..................................................................15
12.3 Trademarks.............................................................15
12.4 Electrostatic Discharge Caution..............................15
12.5 术语表..................................................................... 15
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings(1) ....................................4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements: VCC = 2.5 V ± 0.2 V.................6
6.7 Timing Requirements: VCC = 3.3 V ± 0.3 V.................6
6.8 Timing Requirements: VCC = 5 V ± 0.5 V....................7
6.9 Switching Characteristics: VCC = 2.5 V ± 0.2 V...........7
6.10 Switching Characteristics: VCC = 3.3 V ± 0.3 V.........7
6.11 Switching Characteristics: VCC = 5 V ± 0.5 V............7
6.12 Noise Characteristics(1) ............................................7
6.13 Operating Characteristics......................................... 8
6.14 Typical Characteristics..............................................9
7 Parameter Measurement Information..........................10
Information.................................................................... 15
4 Revision History
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Pin Configuration and Functions
A
1
VCC
14
B
2
3
4
QH
QG
13
12
11
10
QA
QB
QC
QD
PAD
QF
5
6
QE
9
CLR
7
8
GND CLK
图5-1. BQA Package, 14-PIN WQFN (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
A
NO.
1
I
I
Serial input A
Serial input B
Output A
B
2
QA
3
O
O
O
O
G
I
QB
4
Output B
QC
5
Output C
QD
6
Output D
GND
CLK
CLR
QE
7
Ground pin
Storage clock
Storage clear
Output E
8
9
I
10
11
12
13
11
14
O
O
O
O
O
P
—
QF
Output F
QG
Output G
QH
Output H
QH'
QH inverted
Power pin
Thermal pad(2)
VCC
Thermal pad
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
(2) WBQA package only
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6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
VCC Supply voltage
7
–0.5
–0.5
–0.5
–0.5
VI
Input voltage(2)
7
7
V
VO
VO
IIK
Voltage applied to any output in the high-impedance or power-off state(2)
Output voltage(2) (3)
V
VCC + 0.5
V
Input clamp current
VI < 0
mA
mA
mA
mA
°C
–20
–50
±25
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Storage temperature
VO = 0 to VCC
±50
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
±4000
±2000
UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level
C4B
(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over recommended operating free-air temperature range (unless otherwise noted)(1)
MIN
2
MAX
UNIT
VCC
Supply voltage
5.5
V
VCC = 2 V
1.5
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
VCC × 0.7
VCC × 0.7
VCC × 0.7
VIH
High-level input voltage
V
V
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC
VCC = 2 V
µA
–50
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOH
High-level output current
Low-level output current
mA
–6
–12
50
µA
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
2
IOL
6
mA
12
200
Input transition rise or fall rate
Operating free-air temperature
100
ns/V
°C
Δt/Δv
20
TA
125
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74LV164A-Q1
THERMAL METRIC(1)
BQA (WQFN)
14 PINS
88.3
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
90.9
56.8
9.9
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
56.7
33.4
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see IC Package Thermal Metrics
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 125°C
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
TYP
MAX
2 V to
5.5 V
IOH = –50 µA
V
CC –0.1
2.3 V
3 V
2
2.48
3.8
IOH = –2 mA
IOH = –6 mA
IOH = –12 mA
VOH
V
4.5 V
2 V to
5.5 V
IOL = 50 µA
0.1
IOL = 2 mA
IOL = 6 mA
IOL = 12 mA
2.3 V
3 V
0.4
0.44
0.55
VOL
V
4.5 V
0 to
5.5 V
II
VI = 5.5 V or GND
±1
µA
ICC
Ioff
Ci
VI = VCC or GND,
VI or VO = 0 to 5.5 V
VI = VCC or GND
IO = 0
5.5
0
20
5
µA
µA
pF
3.3 V
2.2
6.6 Timing Requirements: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
TA = 25°C
–40°C to 125°C
UNIT
MIN
6
MAX
MIN
6.5
7.5
8.5
3
MAX
CLR low
tw
Pulse duration
ns
CLK high or low
Data before CLK↑
CLR inactive
6.5
6.5
3
tsu
th
Setup time
Hold time
ns
ns
0
Data after CLK↑
–0.5
6.7 Timing Requirements: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
TA = 25°C
–40°C to 125°C
UNIT
MIN
5
MAX
MIN
5
MAX
CLR low
tw
Pulse duration
ns
CLK high or low
Data before CLK↑
CLR inactive
5
5
5
6
tsu
th
Setup time
Hold time
ns
ns
2.5
0
2.5
0
Data after CLK↑
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6.8 Timing Requirements: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
TA = 25°C
–40°C to 125°C
UNIT
MIN
5
MAX
MIN
5
MAX
CLR low
tw
Pulse duration
ns
CLK high or low
Data before CLK↑
CLR inactive
5
5
4.5
2.5
1
4.5
2.5
1
tsu
th
Setup time
Hold time
ns
ns
Data after CLK↑
6.9 Switching Characteristics: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
TA = 25°C
–40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
55
TYP
105
85
MAX
MIN
50
40
1
MAX
CL = 15 pF
CL = 50 pF
fmax
MHz
ns
45
tpd
CLK
CLR
CLK
CLR
Q
Q
Q
Q
9.2
17.6
16
21
18.5
25
CL = 15 pF
CL = 50 pF
tPHL
tpd
8.6
1
11.5
10.8
21.1
19.5
1
ns
tPHL
1
22.5
6.10 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
TA = 25°C
–40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
80
TYP
155
120
6.4
6
MAX
MIN
65
45
1
MAX
CL = 15 pF
CL = 50 pF
fmax
50
tpd
CLK
CLR
CLK
CLR
Q
Q
Q
Q
12.8
12.8
16.3
16.3
16
16
CL = 15 pF
CL = 50 pF
tPHL
tpd
1
8.3
7.9
1
19.5
19.5
ns
tPHL
1
6.11 Switching Characteristics: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
TA = 25°C
–40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
125
85
TYP
220
165
4.5
4.2
6
MAX
MIN
95
65
1
MAX
CL = 15 pF
CL = 50 pF
fmax
tpd
CLK
CLR
CLK
CLR
Q
Q
Q
Q
9
8.6
11.5
11
CL = 15 pF
CL = 50 pF
tPHL
tpd
1
11
1
13
ns
tPHL
5.8
10.6
1
13
6.12 Noise Characteristics(1)
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV164A-Q1
PARAMETER
UNIT
MIN
TYP
0.28
MAX
0.8
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
V
V
–0.22
–0.8
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UNIT
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV164A-Q1
PARAMETER
MIN
TYP
MAX
VOH(V)
VIH(D)
VIL(D)
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low-level dynamic input voltage
3.09
V
V
V
2.31
0.99
(1) Characteristics are for surface-mount packages only.
6.13 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
CL = 50 pF, f = 10 MHz
VCC
TYP
48.1
47.5
UNIT
3.3 V
5 V
Cpd
Power dissipation capacitance
pF
CLR
A
B
CLK
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Clear
Clear
图6-1. Typical Clear, Shift, and Clear Sequences
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6.14 Typical Characteristics
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
-100
-50
0
Temperature
50
100
150
0
1
2
3
Vcc
4
5
6
D001
D002
图6-2. TPD vs. Temperature at 3.3 V
图6-3. TPD vs. VCC at 25°C
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7 Parameter Measurement Information
V
CC
S1
Open
R
= 1 kΩ
L
TEST
/t
S1
From Output
Under Test
Test
From Output
Under Test
GND
Point
t
t
Open
PLH PHL
C
C
L
(see Note A)
t
/t
PLZ PZL
V
CC
L
(see Note A)
/t
PHZ PZH
GND
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
50% V
CC
Input
CC
50% V
50% V
CC
Data Input
0 V
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
CC
Input
CC
CC
CC
0 V
0 V
t
t
t
t
t
PLH
PHL
PZL
PLZ
Output
V
≈V
OH
CC
In-Phase
Output
Waveform 1
50% V
50% V
CC
50% V
CC
CC
V
V
V
+ 0.3 V
OL
S1 at V
CC
(see Note B)
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t 3 ns, t 3 ns.
r ≤ f ≤
O
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
t
and t
and t
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
t
are the same as t
.
en
are the same as t .
G.
t
and t
PLH pd
H. All parameters and waveforms are not applicable to all devices.
图7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LV164A-Q1 devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCC operation.
These devices feature NAND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated
serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data
and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input,
which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is
high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level
transition of the clock (CLK) input.
8.2 Functional Block Diagram
8
CLK
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
1
2
A
B
R
R
R
R
R
R
R
R
9
CLR
3
4
5
6
10
11
12
13
Q
A
Q
Q
C
Q
Q
E
Q
Q
G
Q
H
B
D
F
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
8.3 Feature Description
The wide operating range allows the device to be used in a variety of systems that use different logic levels. The
low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce
stabilizes the performance of non-switching outputs while another output is switching.
8.4 Device Functional Modes
表8-1. Function Table(1)(2)
INPUTS
OUTPUTS
CLR
L
CLK
A
X
X
H
L
B
X
X
H
X
L
QA
L
QB
L
...
QH
L
X
L
H
QA0
H
QB0
QAn
QAn
QAn
QH0
QGn
QGn
QGn
H
↑
↑
↑
H
L
H
X
L
(1) QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before
the indicated steady-state input conditions were established.
(2) QAn, QGn = the level of QA or QG before the most recent ↑
transition of the clock: indicates a 1-bit shift.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LV164A-Q1 is a low drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low-drive and slow-edge rates will minimize overshoot and
undershoot on the outputs.
9.2 Typical Application
VCC
VCC
Seven Segment
R1
C1
QA
QB
QC
QD
QE
QF
QG
QH
g
a
CLR
f
f
b
c
a
A
b
DP
c
g
B
MCU
CLK
e
d
e
d
DP
GND
图9-1. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so consider routing and load conditions to prevent ringing.
9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Rise time and fall time specs. See (Δt/ΔV) in Recommended Operating Conditions.
– Specified high and low level. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
.
• Recommended output conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC
.
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9.2.3 Application Curves
CLR
A
B
CLK
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Clear
Clear
图9-2. Application Timing Diagram
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC
terminals then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor should be installed as close as possible to the power terminal
for best results.
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should
not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. Specified below are the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that should be applied to any particular unused input depends on the function of the device. Generally they
will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally
acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs
section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float
when disabled.
11.2 Layout Example
图11-1. Layout Example
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LV164AQWBQARQ1
ACTIVE
WQFN
BQA
14
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVA164
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV164A-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
Catalog : SN74LV164A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
GENERIC PACKAGE VIEW
BQA 14
2.5 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227145/A
www.ti.com
PACKAGE OUTLINE
BQA0014B
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
A
-
A
3
5
.
0
0
0
SECTION A-A
TYPICAL
0.8
0.6
C
SEATING PLANE
0.08 C
0.05
0.00
1
0.1
2X 0.5
(0.2) TYP
SYMM
7
8
EXPOSED
THERMAL PAD
6
9
(0.16)
TYP
SYMM
15
A
A
1.5 0.1
2X 2
8X 0.5
13
2
0.3
0.2
14X
PIN 1 ID
1
14
0.1
C A B
0.5
0.3
0.05
14X
4227062/B 09/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
BQA0014B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
SYMM
SEE SOLDER MASK
DETAIL
14
1
14X (0.6)
2
14X (0.25)
13
10X (0.5)
(0.5)
15
SYMM
(2.8)
(1.5)
6
9
(R0.05) TYP
(
0.2) TYP
VIA
7
8
(2.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4227062/B 09/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
BQA0014B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.95)
14
1
14X (0.6)
14X (0.25)
2
13
(2.8)
10X (0.5)
15
SYMM
(1.38)
(R0.05) TYP
6
9
7
8
SYMM
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 15
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4227062/B 09/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SN74LV164PW
LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14
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