SN74LV165PWLE [TI]
PARALLEL-LOAD 8-BIT SHIFT REGISTERS; 并联负载8位移位寄存器
| 型号： | SN74LV165PWLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PARALLEL-LOAD 8-BIT SHIFT REGISTERS |
| 文件： | 总8页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
EPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
SN54LV165 . . . J OR W PACKAGE
SN74LV165 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
Typical V
< 0.8 V at V , T = 25°C
(Output Ground Bounce)
OLP
CC
A
SH/LD
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Typical V
< 2 V at V , T = 25°C
(Output V
Undershoot)
OHV
CC
OH
CLK
E
CLK INH
D
A
ESDProtectionExceeds2000VPer
MIL-STD-883C,Method3015;Exceeds200V
UsingMachineModel(C=200pF, R=0)
F
C
G
B
H
A
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Q
SER
H
GND
Q
H
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
SN54LV165 . . . FK PACKAGE
(TOP VIEW)
description
3
2
1
20 19
18
The ’LV165 parallel-load, 8-bit shift registers are
designed for 2.7-V to 5.5-V V operation.
D
4
5
6
7
8
E
F
CC
17
16
15
14
C
When the device is clocked, data is shifted toward
NC
B
NC
G
the serial output Q . Parallel-in access to each
H
stage is provided by eight individual direct data
inputs that are enabled by a low level at the SH/LD
input. The ’LV165 feature a clock inhibit function
A
H
9 10 11 12 13
and a complemented serial output Q .
H
Clocking is accomplished by a low-to-high
transition of the clock (CLK) input while SH/LD is
NC – No internal connection
held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are
interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK
INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held
high. The parallel inputs to the register are enabled while SH/LD is held low independently of the levels of CLK,
CLK INH, or SER.
The SN54LV165 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV165 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
SH/LD
CLK
X
CLK INH
L
X
X
H
↑
Parallel load
H
H
H
H
H
Q
Q
0
0
X
L
Shift
Shift
↑
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
logic diagram (positive logic)
A
B
C
D
E
F
G
H
11
12
13
14
3
4
5
6
1
SH/LD
15
CLK INH
2
CLK
SER
9
7
S
S
S
S
S
S
S
S
Q
Q
H
H
C1
C1
C1
C1
C1
C1
C1
C1
10
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
Pin numbers shown are for D, DB, J, PW, and W packages.
typical shift, load, and inhibit sequences
CLK
CLK INH
SER
L
SH/LD
A
H
L
B
C
H
Data
Inputs
L
D
E
F
H
L
H
H
G
H
L
L
L
Q
H
H
L
H
H
L
H
L
H
Q
H
L
L
H
H
H
Inhibit
Serial Shift
Load
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
20 mA
50 mA
25 mA
50 mA
I
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . . 1.30 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
DB package . . . . . . . . . . . . . . . . . . . 0.55 W
PW package . . . . . . . . . . . . . . . . . . . 0.5 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 4)
SN54LV165
SN74LV165
UNIT
V
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
Supply voltage
5.5
5.5
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
High-level input voltage
V
IH
3.15
3.15
0.8
0.8
V
IL
Low-level input voltage
V
1.65
1.65
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
–6
V
CC
–6
O
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
6
–12
6
I
12
12
100
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
100
125
0
ns/V
T
A
–55
–40
°C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV165
MIN TYP MAX
–0.2
SN74LV165
MIN TYP MAX
–0.2
†
PARAMETER
TEST CONDITIONS
UNIT
V
CC
I
I
I
I
I
I
= –100 µA
MIN to MAX
3 V
V
V
OH
OH
OH
OL
OL
OL
CC
2.4
3.6
CC
2.4
3.6
V
V
= –6 mA
= –12 mA
= 100 µA
= 6 mA
V
OH
4.5 V
MIN to MAX
3 V
0.2
0.4
0.55
±1
0.2
0.4
0.55
±1
V
OL
= 12 mA
4.5 V
3.6 V
I
I
V = V
or GND
or GND,
µA
I
I
CC
CC
5.5 V
±1
±1
3.6 V
20
20
V = V
I = 0
O
µA
µA
pF
CC
I
5.5 V
20
20
One input at V
CC
– 0.6 V,
or GND
I
3 V to 3.6 V
500
500
CC
Other inputs at V
CC
3.3 V
5 V
2.5
3
2.5
3
C
V = V
or GND
CC
i
I
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV165
V = 5.5 V
CC
± 0.5 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
50
40
30
MHz
ns
clock
CLK high or low
14
14
10
8
18
18
13
11
12
12
6
22
22
17
14
15
17
5
w
SH/LD low
SH/LD high before CLK↑
SER before CLK↑
t
t
ns
ns
Setup time
Hold time
su
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
Parallel data after SH/LD↑
10
8
6
h
6
6
5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN74LV165
V = 5.5 V
CC
± 0.5 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
50
40
30
MHz
ns
clock
CLK high or low
14
14
10
8
18
18
13
11
12
12
6
22
22
17
14
15
17
5
w
SH/LD low
SH/LD high before CLK↑
SER before CLK↑
t
t
ns
ns
Setup time
Hold time
su
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
Parallel data after SH/LD↑
10
8
6
h
6
6
5
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LV165
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
= 5.5 V ± 0.5 V
V
CC
= 3.3 V ± 0.3 V
V
CC
= 2.7 V
MAX
UNIT
MHz
ns
CC
MIN
TYP
90
MAX
MIN
TYP
75
MAX
MIN
f
t
50
40
30
max
CLK
SH/LD
H
20
24
24
20
20
38
36
29
47
44
36
Q
or Q
H
19
19
H
pd
15
15
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN74LV165
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
= 5.5 V ± 0.5 V
V
CC
= 3.3 V ± 0.3 V
V
CC
= 2.7 V
MAX
UNIT
MHz
ns
CC
MIN
TYP
90
MAX
MIN
TYP
75
MAX
MIN
f
t
50
40
30
max
CLK
SH/LD
H
20
24
24
20
20
38
36
29
47
44
36
Q
or Q
H
19
19
H
pd
15
15
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
V
TYP
UNIT
CC
3.3 V
5 V
33
C
Power dissipation capacitance
C
pF
pd
L
57
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
V
z
TEST
S1
S1
Open
1 kΩ
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
t
V
z
GND
GND
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
1 kΩ
(see Note A)
WAVEFORM
CONDITION
V
= 4.5 V
V
= 2.7 V
CC
to 5.5 V
CC
to 3.6 V
1.5 V
2.7 V
6 V
V
m
0.5 × V
CC
V
i
V
z
V
CC
LOAD CIRCUIT
2 × V
CC
V
i
V
m
Timing Input
0 V
t
w
t
t
su
h
V
i
V
i
V
m
V
m
Input
V
m
V
m
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
i
i
Output
Control
V
V
m
m
Input
V
m
V
m
0 V
0 V
V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
0.5 × V
z
OH
V
V
V
m
V
m
m
Output
Output
V
+ 0.3 V
– 0.3 V
S1 at V
(see Note B)
OL
z
V
OL
V
OL
t
PHZ
t
PLH
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
V
V
m
m
m
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SSOP
SOIC
Drawing
SN74LV165D
SN74LV165DBLE
SN74LV165DR
OBSOLETE
OBSOLETE
OBSOLETE
D
DB
D
16
16
16
16
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
SN74LV165PWLE
OBSOLETE TSSOP
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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Copyright 2005, Texas Instruments Incorporated
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