SN74LV273APWRG4 [TI]
OCTAL D-TYPE FLIP-FLOPS WITH CLEAR; 八路D型触发器与Clear型号: | SN74LV273APWRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR |
文件: | 总17页 (文件大小:513K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁꢇ ꢃꢄꢅ ꢆꢇ ꢈꢉ
ꢋ ꢌꢍꢉꢄ ꢎꢏꢍ ꢐꢑ ꢒ ꢓ ꢄ ꢔꢑ ꢏ ꢓꢄꢋ ꢑ ꢀ
ꢕ ꢔꢍꢖ ꢌ ꢄꢒ ꢉꢗ
SCLS399J − APRIL 1998 − REVISED APRIL 2005
D
D
D
D
D
2-V to 5.5-V V
Operation
D
D
D
Support Mixed-Mode Voltage Operation on
All Ports
CC
Max t of 10.5 ns at 5 V
pd
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
I
Supports Partial-Power-Down Mode
off
− 1000-V Charged-Device Model (C101)
Operation
SN54LV273A . . . J OR W PACKAGE
SN74LV273A . . . DB, DGV, DW, NS,
OR PW PACKAGE
SN74LV273A . . . RGY PACKAGE
(TOP VIEW)
SN54LV273A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
20
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
3
2
1
20 19
18
1Q
1D
2D
2Q
3Q
3D
4D
4Q
19 8Q
2
3
4
5
6
7
8
9
2D
2Q
3Q
3D
4D
8D
17 7D
4
5
6
7
8
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
18
17
16
15
14
13
12
8D
7D
7Q
6Q
6D
5D
5Q
16
15
14
7Q
6Q
6D
9 10 11 12 13
10
11
GND
description/ordering information
The ’LV273A devices are octal D-type flip-flops designed for 2-V to 5.5-V V
operation.
CC
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74LV273ARGYR
SN74LV273ADW
SN74LV273ADWR
SN74LV273ANSR
SN74LV273ADBR
SN74LV273APW
SN74LV273APWR
SN74LV273APWT
SN74LV273ADGVR
SNJ54LV273AJ
QFN − RGY
SOIC − DW
Reel of 1000
Tube of 25
LV273A
LV273A
LV273A
74LV273A
LV273A
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
SOP − NS
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 20
TSSOP − PW
LV273A
TVSOP − DGV
CDIP − J
LV273A
SNJ54LV273AJ
SNJ54LV273AW
SNJ54LV273AFK
CFP − W
Tube of 85
SNJ54LV273AW
SNJ54LV273AFK
−55°C to 125°C
LCCC − FK
Tube of 55
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢘ ꢁ ꢄꢒꢀꢀ ꢋ ꢍꢖ ꢒꢗꢕ ꢔꢀ ꢒ ꢁ ꢋꢍꢒꢎ ꢙꢚ ꢛꢜ ꢝꢞꢟ ꢠꢡꢢ ꢣꢙ ꢟꢞ ꢣꢙꢤ ꢛꢣꢜ ꢑꢗ ꢋ ꢎ ꢘ ꢌꢍ ꢔꢋ ꢁ
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ꢩ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢇꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢍꢉ ꢄ ꢎ ꢏꢍ ꢐꢑꢒ ꢓꢄ ꢔ ꢑ ꢏꢓꢄ ꢋꢑ ꢀ
ꢕꢔ ꢍ ꢖ ꢌ ꢄ ꢒꢉ ꢗ
SCLS399J − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
These devices are positive-edge-triggered flip-flops with direct clear (CLR) input. Information at the data (D)
inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time
of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has
no effect at the output.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
CLR
L
CLK
X
D
X
H
L
L
H
L
H
↑
H
↑
H
L
X
Q
0
logic diagram (positive logic)
1D
2D
3D
4D
5D
13
6D
14
7D
17
8D
18
3
4
7
8
11
CLK
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
R
R
R
R
R
R
R
R
1
CLR
2
5
6
9
12
5Q
15
6Q
16
7Q
19
8Q
1Q
2Q
3Q
4Q
2
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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢋ ꢌꢍꢉꢄ ꢎꢏꢍ ꢐꢑ ꢒ ꢓ ꢄ ꢔꢑ ꢏ ꢓꢄꢋ ꢑ ꢀ
ꢕ ꢔꢍꢖ ꢌ ꢄꢒ ꢉꢗ
SCLS399J − APRIL 1998 − REVISED APRIL 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance or
power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢇꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢍꢉ ꢄ ꢎ ꢏꢍ ꢐꢑꢒ ꢓꢄ ꢔ ꢑ ꢏꢓꢄ ꢋꢑ ꢀ
ꢕꢔ ꢍ ꢖ ꢌ ꢄ ꢒꢉ ꢗ
SCLS399J − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV273A
SN74LV273A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
5.5
V
V
V
× 0.3
× 0.3
× 0.3
5.5
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV273A
SN74LV273A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
V
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I
O
= 0
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
2
2
i
I
CC
ꢑ
ꢗ
ꢋ
ꢎ
ꢘ
ꢌ
ꢍ
ꢑ
ꢗ
ꢒ
ꢅ
ꢔ
ꢒ
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ꢛ
ꢣ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢮ ꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢯ ꢢ ꢩ ꢞꢧ ꢡꢢ ꢣ ꢙꢪ ꢌ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢ
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ꢟ ꢚ ꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞ ꢝꢠꢟ ꢙꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢯ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢋ ꢌꢍꢉꢄ ꢎꢏꢍ ꢐꢑ ꢒ ꢓ ꢄ ꢔꢑ ꢏ ꢓꢄꢋ ꢑ ꢀ
ꢕ ꢔꢍꢖ ꢌ ꢄꢒ ꢉꢗ
SCLS399J − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV273A SN74LV273A
A
UNIT
MIN
6.5
7
MAX
MIN
7
MAX
MIN
7
MAX
CLR low
t
w
Pulse duration
ns
CLK high or low
Data
8.5
10.5
4
8.5
10.5
4
8.5
4
t
t
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
CLR inactive
0.5
1
1
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV273A SN74LV273A
A
UNIT
MIN
5
MAX
MIN
6
MAX
MIN
6
MAX
CLR low
t
w
Pulse duration
ns
CLK high or low
Data
5
6.5
6.5
2.5
1
6.5
6.5
2.5
1
5.5
2.5
1
t
t
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
CLR inactive
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV273A SN74LV273A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLR low
t
w
Pulse duration
ns
CLK high or low
Data
5
5
5
4.5
2
4.5
2
4.5
2
t
t
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
CLR inactive
1
1
1
h
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
95*
SN54LV273A SN74LV273A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
55*
45
MAX
MIN
45*
40
MAX
MIN
45
40
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
max
75
t
t
t
t
t
CLK
CLR
CLK
CLR
Q
Q
Q
Q
10.4* 18.3*
1* 20.5*
20.5
21
pd
C
C
= 15 pF
= 50 pF
L
L
10.3*
12.9
13.1
19*
22.1
22.8
2
1*
1
21*
25
1
PHL
pd
1
25
1
25.5
1
25.5
2
ns
PHL
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢑ
ꢗ
ꢋ
ꢎ
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ꢗ
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ꢅ
ꢔ
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ꢣ
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ꢣ
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ꢝꢢ ꢜ ꢛ ꢮꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢯ ꢢ ꢩꢞ ꢧꢡꢢ ꢣꢙꢪ ꢌ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢟ
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ꢣ
ꢜ
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ꢢ
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ꢣ
ꢮ
ꢞ
ꢤ
ꢩ
ꢜ
ꢪ
ꢍ
ꢢ
ꢫ
ꢤ
ꢜ
ꢔ
ꢣ
ꢜ
ꢙ
ꢦ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞꢝ ꢠꢟꢙ ꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
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ꢜ
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ꢦ
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5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢇꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢍꢉ ꢄ ꢎ ꢏꢍ ꢐꢑꢒ ꢓꢄ ꢔ ꢑ ꢏꢓꢄ ꢋꢑ ꢀ
ꢕꢔ ꢍ ꢖ ꢌ ꢄ ꢒꢉ ꢗ
SCLS399J − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV273A SN74LV273A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
75*
50
MAX
MIN
65*
45
1*
MAX
MIN
65
45
1
MAX
C
C
= 15 pF
= 50 pF
140*
110
L
L
f
max
t
t
t
t
t
CLK
CLR
CLK
CLR
Q
Q
Q
Q
7.1* 13.6*
6.9* 13.6*
16*
16*
16
16
pd
C
C
= 15 pF
= 50 pF
L
L
1*
1
PHL
pd
9.1
8.7
17.1
17.1
1.5
1
19.5
19.5
1
19.5
19.5
1.5
1
1
ns
PHL
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
205*
160
4.8*
4.7*
6.2
SN54LV273A SN74LV273A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
120*
80
MAX
MIN
100*
70
MAX
MIN
100
70
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
max
t
t
t
t
t
CLK
CLR
CLK
CLR
Q
Q
Q
Q
9*
8.5*
11
1* 10.5*
10.5
10
pd
C
C
= 15 pF
= 50 pF
L
L
1*
1
10*
12.5
12
1
PHL
pd
1
12.5
12
6
10.5
1
1
1
ns
PHL
sk(o)
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 6)
CC
L
A
SN74LV273A
PARAMETER
UNIT
MIN
TYP
0.4
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.4
2.9
−0.8
OL
OH
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
15.9
17.1
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
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ꢞ
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ꢤ
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ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢮ ꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢯ ꢢ ꢩ ꢞꢧ ꢡꢢ ꢣ ꢙꢪ ꢌ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢙ
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ꢛ
ꢣ
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ꢥ
ꢞ
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ꢤ
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ꢮ
ꢞ
ꢤ
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ꢫ
ꢤ
ꢜ
ꢔ
ꢣ
ꢜ
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ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚ ꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞ ꢝꢠꢟ ꢙꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢯ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢋ ꢌꢍꢉꢄ ꢎꢏꢍ ꢐꢑ ꢒ ꢓ ꢄ ꢔꢑ ꢏ ꢓꢄꢋ ꢑ ꢀ
ꢕ ꢔꢍꢖ ꢌ ꢄꢒ ꢉꢗ
SCLS399J − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
CC
V
CC
Output
Control
50% V
CC
50% V
CC
50% V
CC
50% V
CC
0 V
0 V
t
t
PZL
PLZ
t
t
t
PHL
PLH
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
SN74LV273ADBR
SN74LV273ADBRE4
SN74LV273ADGVR
SN74LV273ADGVRE4
SN74LV273ADW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
TVSOP
TVSOP
SOIC
DB
DGV
DGV
DW
DW
DW
DW
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV273ADWE4
SN74LV273ADWR
SN74LV273ADWRE4
SN74LV273ANSR
SN74LV273ANSRG4
SN74LV273APW
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
PW
PW
PW
PW
PW
RGY
ZQN
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV273APWE4
SN74LV273APWR
SN74LV273APWRE4
SN74LV273APWRG4
SN74LV273APWT
SN74LV273APWTE4
SN74LV273ARGYR
SN74LV273AZQNR
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
VFBGA
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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