SN74LV374ATPWRG4Q1 [TI]
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS; 八路边沿触发D型触发器具有三态输出型号: | SN74LV374ATPWRG4Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS |
文件: | 总11页 (文件大小:199K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74LV374A-Q1
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCLS468C − FEBRUARY 2003 − REVISED JANUARY 2008
PW PACKAGE
(TOP VIEW)
D
D
Qualified for Automotive Applications
Typical V (Output Ground Bounce)
OLP
<0.8 V at V = 3.3 V, T = 25°C
CC
A
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VCC
1
2
3
4
5
6
7
8
9
10
20
D
D
D
D
Typical V
(Output V Undershoot)
19 8Q
18 8D
OHV
OH
>2.3 V at V = 3.3 V, T = 25°C
CC
A
17
16
15
14
13
12
11
7D
7Q
6Q
6D
5D
5Q
CLK
Supports Mixed-Mode Voltage Operation on
All Ports
I
off
Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
GND
− 1000-V Charged-Device Model (C101)
description/ordering information
The SN74LV374A is an octal edge-triggered D-type flip-flop designed for 2-V to 5.5-V V operation.
CC
This device features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
PACKAGE
−40°C to 105°C
TSSOP − PW Tape and reel
SN74LV374ATPWRQ1
LV374ATQ
†
‡
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LV374A-Q1
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCLS468C − FEBRUARY 2003 − REVISED JANUARY 2008
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK
OUTPUT
Q
OE
L
D
H
L
↑
↑
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
2
1Q
3
1D
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance or
power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
O
O
CC
Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
CC
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
JA
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LV374A-Q1
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCLS468C − FEBRUARY 2003 − REVISED JANUARY 2008
recommended operating conditions (see Note 4)
MIN
2
MAX
UNIT
V
Supply voltage
5.5
V
CC
IH
V
V
V
V
V
V
V
V
= 2 V
1.5
CC
CC
CC
CC
CC
CC
CC
CC
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
CC
CC
CC
V
High-level input voltage
V
× 0.7
× 0.7
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
CC
CC
CC
V
IL
Low-level input voltage
V
V
× 0.3
× 0.3
V
V
Input voltage
0
0
0
5.5
I
High or low state
3-state
V
CC
Output voltage
V
O
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
μA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
−8
mA
−16
50
μA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
OL
8
mA
16
200
100
20
Δt/Δv Input transition rise or fall rate
ns/V
T
A
Operating free-air temperature
−40
105
°C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
−0.1
TYP
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
= −50 μA
= −2 mA
= −8 mA
= −16 mA
= 50 μA
= 2 mA
2 V to 5.5 V
2.3 V
V
CC
OH
OH
OH
OH
OL
OL
OL
OL
2
2.48
3.8
V
V
V
OH
3 V
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
V
OL
= 8 mA
3 V
= 16 mA
4.5 V
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
μA
μA
μA
μA
pF
I
I
V
= V or GND
5
OZ
O
CC
I
I
V = V or GND,
I = 0
O
5.5 V
20
CC
off
I
CC
V or V = 0 to 5.5 V
0
5
I
O
C
V = V or GND
3.3 V
2.9
i
I
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LV374A-Q1
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCLS468C − FEBRUARY 2003 − REVISED JANUARY 2008
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V
(unless otherwise noted) (see Figure 1)
T = 25°C
A
MIN
MAX
UNIT
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
5.5
4.5
2
ns
ns
ns
4.5
2
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V
(unless otherwise noted) (see Figure 1)
T = 25°C
A
MIN
MAX
UNIT
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
5
3
2
ns
ns
ns
3
2
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
T = 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
MIN
MAX
UNIT
MIN
TYP
110
8.3
MAX
f
t
55
50
1
MHz
max
CLK
OE
Q
Q
Q
16.2
14.5
14
18.5
17.5
16
pd
t
t
t
7.7
1
C = 50 pF
L
en
ns
5.9
1
OE
dis
1.5
sk(o)
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
T = 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
MIN
MAX
UNIT
MIN
TYP
170
5.9
5.5
4
MAX
f
t
85
75
1
MHz
max
CLK
OE
Q
Q
Q
10.1
9.6
8.8
1
13.5
13
pd
t
t
t
1
C = 50 pF
L
en
ns
1
10
OE
dis
sk(o)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LV374A-Q1
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCLS468C − FEBRUARY 2003 − REVISED JANUARY 2008
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
PARAMETER
MIN
TYP
0.6
MAX
0.8
UNIT
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
Quiet output, maximum dynamic V
V
V
V
V
V
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.5
2.9
−0.8
OL
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
C = 50 pF, f = 10 MHz
V
TYP
21.1
22.8
UNIT
CC
3.3 V
C
Power dissipation capacitance
Outputs enabled
pF
pd
L
5 V
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LV374A-Q1
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCLS468C − FEBRUARY 2003 − REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
GND
R = 1 kΩ
L
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
Open
PLH PHL
t
C
C
L
/t
V
CC
L
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
Input
Input
CC
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
CC
CC
CC
CC
0 V
0 V
t
t
PZL
PLZ
t
t
t
PHL
PLH
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
S1 at V
CC
V
V
+ 0.3 V
OL
V
OL
V
OL
(see Note B)
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PHL
PHZ
dis
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LV374ATPWRG4Q1
SN74LV374ATPWRQ1
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV374A-Q1 :
Catalog: SN74LV374A
•
Enhanced Product: SN74LV374A-EP
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
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