SN74LV374ATPWRG4 [TI]
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS; 八路边沿触发D型触发器具有三态输出
| 型号： | SN74LV374ATPWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS |
| 文件： | 总21页 (文件大小：874K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV374AT
www.ti.com
SCES632 –JUNE 2010
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Check for Samples: SN74LV374AT
1
FEATURES
•
•
•
•
Inputs Are TTL-Voltage Compatible
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
4.5-V to 5.5-V VCC Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical tpd of 4.9 ns at 5 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 5 V, TA = 25°C
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
•
•
Typical VOHV (Output VOH Undershoot) >2.3 V
at VCC = 5 V, TA = 25°C
1000-V Charged-Device Model (C101)
Support Mixed-Mode Voltage Operation on All
Ports
DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VCC
8Q
8D
7D
7Q
6Q
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
1
20
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1Q
1D
2D
2Q
3Q
3D
4D
4Q
8Q
8D
7D
7Q
6Q
6D
5D
5Q
14 6D
13 5D
12 5Q
11 CLK
GND 10
10
11
DESCRIPTION
The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LV374AT
SCES632 –JUNE 2010
www.ti.com
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
VV374
QFN – RGY
SOIC – DW
Reel of 1000
SN74LV374ATRGYR
SN74LV374ATDW
SN74LV374ATDWR
SN74LV374ATNSR
SN74LV374ATDBR
SN74LV374ATPW
SN74LV374ATPWR
SN74LV374ATPWT
Tube of 25
LV374AT
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
SOP – NS
74LV374AT
LV374AT
–40°C to 125°C
SSOP – DB
TSSOP – PW
Reel of 2000
Tube of 250
LV374AT
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
L
X
X
X
Q0
Z
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE
11
3
CLK
C1
1D
2
1Q
1D
To Seven Other Channels
2
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Product Folder Link(s): SN74LV374AT
SN74LV374AT
www.ti.com
SCES632 –JUNE 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range(2) (3)
7
7
7
V
V
VO
VO
IIK
–0.5 VCC + 0.5
V
Input clamp current
VI < 0 or VI > VCC
VO < 0 or VO > VCC
VO = 0 to VCC
±20
±50
±35
±70
70
mA
mA
mA
mA
IOK
IO
Output clamp current
Continuous output current
Continuous current through VCC or GND
DB package(4)
DW package(4)
NS package(4)
PW package(4)
RGY package(5)
58
qJA
Package thermal impedance
Storage temperature range
60 °C/W
83
37
Tstg
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
4.5
2
MAX UNIT
VCC
VIH
VIL
VI
Supply voltage
5.5
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
0.8
5.5
VCC
5.5
–16
16
0
0
0
High or low state
3-state
VO
Output voltage
V
IOH
IOL
High-level output current
Low-level output current
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
mA
mA
ns/V
°C
Δt/Δv Input transition rise or fall rate
TA Operating free-air temperature
20
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2010, Texas Instruments Incorporated
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SN74LV374AT
SCES632 –JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA = –40°C
to 85°C
TA = –40°C
to 125°C
TA = 25°C
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN TYP
MAX
MIN
4.4
MAX
MIN MAX
4.4
IOH = –50 mA
4.5 V
4.5 V
4.4
3.8
4.5
VOH
V
V
IOH = –16 mA
3.8
3.8
IOL = 50 mA
4.5 V
0
0.1
0.55
±0.1
±0.25
2
0.1
0.55
±1
0.1
VOL
IOL = 16 mA
4.5 V
0.55
±1
II
VI = 5.5 V or GND
VO = VCC or GND
VI = VCC or GND,
One input at 3.4 V,
Other inputs at VCC or GND
VI or VO = 0 to 5.5 V
VI = VCC or GND
0 to 5.5 V
5.5 V
mA
mA
mA
IOZ
ICC
±2.5
20
±2.5
20
IO = 0
5.5 V
(1)
ΔICC
5.5 V
0
40
50
5
50
5
mA
Ioff
Ci
0.5
mA
4
pF
(1) This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC
.
TIMING REQUIREMENTS
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = –40°C
to 85°C
TA = –40°C
to 125°C
TA = 25°C
LOAD
CAPACITANCE
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
CL = 15 pF
CL = 50 pF
90
85
80
75
70
65
fclock Clock frequency
MHz
tw
tsu
th
Pulse duration, CLK high or low
6.5
2.5
2.5
8.5
2.5
2.5
8.5
5
ns
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
2.5
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = –40°C
to 85°C
TA = –40°C
to 125°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN TYP
MAX
MIN
80
75
1
MAX MIN
MAX
CL = 15 pF
CL = 50 pF
90
85
140
150
4.9
4.6
3.4
5.9
5.5
4
70
65
1
fmax
MHz
tpd
ten
CLK
OE
Q
Q
Q
Q
Q
Q
3
8.1
7.6
6.8
10.1
9.6
8.8
1
10.5
11.5
8
11
12
9
CL = 15 pF
3.2
1.7
4.2
4.5
2.4
1
1
ns
ns
tdis
tpd
OE
1
1
CLK
OE
1
11.5
12.5
12
1
13
13
12.5
1
ten
1
1
CL = 50 pF
tdis
tsk(o)
OE
1
1
1
4
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SN74LV374AT
www.ti.com
SCES632 –JUNE 2010
NOISE CHARACTERISTICS(1)
VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER
Quiet output, maximum dynamic VOL
MIN
TYP
1.3
MAX
1.6
UNIT
VOL(P)
VOL(V)
VOH(V)
VIH(D)
VIL(D)
V
V
V
V
V
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low-level dynamic input voltage
–0.3
4.6
–1.65
2
0.8
(1) Characteristics are for surface-mount packages only.
OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
CL = 50 pF, f = 10 MHz
TYP
UNIT
Cpd
Power dissipation capacitance
Outputs enabled
42.5
pF
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s): SN74LV374AT
SN74LV374AT
SCES632 –JUNE 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
GND
R
L
= 1 kΩ
TEST
/t
S1
From Output
Under Test
C
Test
Point
From Output
Under Test
t
t
Open
PLH PHL
C
L
t
/t
V
CC
GND
L
PLZ PZL
(see Note A)
(see Note A)
/t
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
PZL
PLZ
t
t
t
PHL
PLH
Output
Waveform 1
≈V
V
CC
OH
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
S1 at V
CC
V
V
+ 0.3 V
OL
V
OL
V
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
50% V
CC
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PHL
PHZ
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuits and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LV374ATDB
SN74LV374ATDBG4
SN74LV374ATDBR
SN74LV374ATDBRG4
SN74LV374ATDW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SO
DB
DB
DB
DB
DW
DW
DW
DW
NS
NS
NS
NS
PW
PW
PW
PW
PW
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
70
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
2000
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74LV374ATDWG4
SN74LV374ATDWR
SN74LV374ATDWRG4
SN74LV374ATNS
25
Green (RoHS
& no Sb/Br)
2000
2000
40
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74LV374ATNSG4
SN74LV374ATNSR
SN74LV374ATNSRG4
SN74LV374ATPW
SO
40
Green (RoHS
& no Sb/Br)
SO
2000
2000
70
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
SN74LV374ATPWE4
SN74LV374ATPWG4
SN74LV374ATPWR
SN74LV374ATPWRE4
70
Green (RoHS
& no Sb/Br)
70
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LV374ATPWRG4
SN74LV374ATPWT
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
20
20
20
20
20
20
2000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
SN74LV374ATPWTE4
SN74LV374ATPWTG4
SN74LV374ATRGYR
SN74LV374ATRGYRG4
PW
250
Green (RoHS
& no Sb/Br)
PW
250
Green (RoHS
& no Sb/Br)
RGY
RGY
3000
3000
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2011
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV374ATDBR
SN74LV374ATDWR
SN74LV374ATNSR
SN74LV374ATPWR
SN74LV374ATPWT
SN74LV374ATRGYR
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
20
2000
2000
2000
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
16.4
24.4
24.4
16.4
16.4
12.4
8.2
10.8
8.2
7.5
13.0
13.0
7.1
2.5
2.7
2.5
1.6
1.6
1.6
12.0
12.0
12.0
8.0
16.0
24.0
24.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
SO
TSSOP
TSSOP
VQFN
PW
PW
RGY
6.95
6.95
3.8
7.1
8.0
3000
4.8
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV374ATDBR
SN74LV374ATDWR
SN74LV374ATNSR
SN74LV374ATPWR
SN74LV374ATPWT
SN74LV374ATRGYR
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
20
2000
2000
2000
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
45.0
45.0
38.0
38.0
35.0
SO
TSSOP
TSSOP
VQFN
PW
PW
RGY
3000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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