SN74LV4040A-EP [TI]
12 BIT ASYNCHRONOUS BINARY COUNTERS; 12位异步二进制计数器
| 型号： | SN74LV4040A-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 BIT ASYNCHRONOUS BINARY COUNTERS |
| 文件： | 总12页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030–SEPTEMBER 2007
1
FEATURES
•
Controlled Baseline
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
–
–
–
One Assembly
Test Site
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
One Fabrication Site
ESD Protection Exceeds JESD 22
•
•
Extended Temperature Performance of –55°C
to 125°C
–
–
–
xxx
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Enhanced Diminishing Manufacturing Sources
(DMS) Support
1000-V Charged-Device Model (C101)
•
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
SN74LV4040A . . . PW PACKAGE
(TOP VIEW)
2-V to 5.5-V VCC Operation
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
QL
QF
VCC
QK
QJ
1
2
3
4
5
6
7
8
16
15
14
•
•
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
QE
QG
13 QH
Support Mixed-Mode Voltage Operation on All
Ports
12
11
10
9
QD
QI
QC
CLR
CLK
QA
•
•
•
•
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
QB
GND
Extremely Low Input Current
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
The SN74LV4040A device is a 12 bit asynchronous binary counter with the outputs of all stages available
externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The
count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits,
counter controls, and frequency-dividing circuits.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the devices when they are powered down.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
LW040A
–55°C to 125°C
TSSOP – PW
Reel of 2000
SN74LV4040AMPWREP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030–SEPTEMBER 2007
FUNCTION TABLE
(each buffer)
INPUTS
FUNCTION
CLK
CLR
L
↑
↓
No change
L
Advance to next stage
All outputs L
X
H
LOGIC DIAGRAM (POSITIVE LOGIC)
11
10
CLR
CLK
R
R
R
R
R
T
T
T
T
T
9
7
6
5
3
QA
QC
QD
QE
QB
R
R
R
R
R
R
R
T
T
T
T
T
T
T
2
4
13
12
14
15
1
QF
QG
QH
QI
QJ
QK
QL
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range(2)(3)
7
V
7
7
V
V
VO
VO
IIK
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–20
–50
±25
±50
108
mA
mA
mA
mA
°C/W
°C
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Package thermal impedance(4)
Storage temperature range
VO = 0 to VCC
θJA
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Product Folder Link(s): SN74LV4040A-EP
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030–SEPTEMBER 2007
Recommended Operating Conditions(1)
MIN
2
MAX
UNIT
VCC
Supply voltage
5.5
V
VCC = 2 V
1.5
VCC = 2.3 to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2 V
V
V
V
CC × 0.7
CC × 0.7
CC × 0.7
VIH
High-level input voltage
V
V
0.5
CC × 0.3
CC × 0.3
CC × 0.3
5.5
VCC = 2.3 to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 to 5.5 V
V
V
V
VIL
Low-level input voltage
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC
–50
–2
VCC = 2 V
VCC = 2.3 to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2 V
IOH
High-level output current
Low-level output current
mA
–6
–12
50
μA
VCC = 2.3 to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 to 5.5 V
2
IOL
6
mA
12
200
100
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
–55
125
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V to 5.5 V
2.3 V
MIN
VCC – 0.1
2
TYP
MAX
UNIT
IOH = –50 μA
IOH = –2 mA
IOH = –6 mA
VOH
V
3 V
2.48
IOH = –12 mA
4.5 V
3.8
IOL = 50 μA
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
±1
IOL = 2 mA
VOL
V
IOL = 6 mA
3 V
IOL = 12 mA
4.5 V
II
VI = 5.5 V or GND
VI = VCC or GND, IO = 0
VI or VO = 0 to 5.5 V
VI = VCC or GND
0 to 5.5 V
5.5 V
μA
μA
μA
pF
ICC
Ioff
Ci
20
0
5
3.3 V
1.9
Copyright © 2007, Texas Instruments Incorporated
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SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030–SEPTEMBER 2007
Timing Requirements
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX UNIT
MIN
7
MAX
CLK high or low
CLR high
7
6.5
6.5
tw
Pulse duration
Setup time
ns
ns
6.5
6.5
tsu
CLR inactive before CLK↓
Timing Requirements
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX UNIT
MIN
5
MAX
CLK high or low
CLR high
5
5
5
tw
Pulse duration
Setup time
ns
ns
5
tsu
CLR inactive before CLK↓
5
Timing Requirements
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX UNIT
MIN
5
MAX
CLK high or low
CLR high
5
5
5
tw
Pulse duration
Setup time
ns
ns
5
tsu
CLR inactive before CLK↓
5
Switching Characteristics
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
95
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX UNIT
MIN
MAX
fmax
tPLH
tPHL
tPHL
Δtpd
CL = 50 pF
CL = 50 pF
40
35
1
MHz
10.5
10.5
11.7
1.7
24.1
24.1
24.5
11.1
28
ns
28
CLK
QA
1
CLR
Qn
Any Q
Qn+1
CL = 50 pF
CL = 50 pF
1
28
ns
ns
10.8
4
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Product Folder Link(s): SN74LV4040A-EP
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030–SEPTEMBER 2007
Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
130
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX UNIT
MIN
MAX
fmax
tPLH
tPHL
tPHL
Δtpd
CL = 50 pF
CL = 50 pF
55
50
1
MHz
7.5
15.4
15.4
16.3
5.4
17.5
ns
CLK
QA
7.5
1
17.5
CLR
Qn
Any Q
Qn+1
CL = 50 pF
CL = 50 pF
9
1
18.5
6.6
ns
ns
1.2
Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
185
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX UNIT
MIN
MAX
fmax
tPLH
tPHL
tPHL
Δtpd
CL = 50 pF
CL = 50 pF
95
80
1
MHz
5.3
9.3
9.3
10.5
ns
CLK
QA
5.3
1
10.5
CLR
Qn
Any Q
Qn+1
CL = 50 pF
CL = 50 pF
6.8
10.6
4.0
1
12
ns
ns
0.8
5.5
Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C
(1)
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
VIH(D)
VIL(D)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
High-level dynamic input voltage
Low-level dynamic input voltage
0.5
0.8
V
V
V
V
–0.5
–0.8
2.31
0.99
(1) Characteristics are for surface-mount packages only.
Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
CL = 50 pF, f = 10 MHz
VCC
TYP UNIT
3.3 V
5 V
11.9
pF
Cpd
Power dissipation capacitance
13.1
Copyright © 2007, Texas Instruments Incorporated
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SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030–SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION
VCC
Open
GND
S1
RL = 1 k W
TEST
S1
From Output
Under Test
Test
From Output
Under Test
Point
tPLH/tPHL
tPLZ/tPZL
Open
VCC
CL
(see Note A)
CL
(see Note A)
tPHZ/tPZH
GND
VCC
Open Drain
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
VCC
50% VCC
th
Timing Input
0 V
tw
tsu
VCC
VCC
0 V
50% VCC
50% VCC
Input
50% VCC
50% VCC
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC
0 V
Output
50% VCC
50% VCC
50% VCC
50% VCC
Input
Control
0 V
tPZL
tPLZ
tPLH
tPHL
Output
VOH
»VCC
Waveform 1
In-Phase
Output
50% VCC
50% VCC
50% VCC
S1 at VCC
VOL + 0.3 V
VOL
VOL
(see Note B)
tPHL
tPLH
tPZH
tPHZ
Output
Waveform 2
S1 at GND
VOH
50% VCC
VOL
VOH
Out-of-Phase
Output
VOH - 0.3 V
50% VCC
50% VCC
»0 V
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 1 Mhz, ZO = 50 W, tr £ 3 ns, tf £ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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Product Folder Link(s): SN74LV4040A-EP
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74LV4040AMPWREP
V62/07630-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
PW
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4040A-EP :
Catalog: SN74LV4040A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV4040AMPWREP TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
SN74LV4040AMPWREP
2000
Pack Materials-Page 2
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