SN74LV4040ADGVRG4 [TI]
LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16, GREEN, PLASTIC, TVSOP-16;
| 型号： | SN74LV4040ADGVRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16, GREEN, PLASTIC, TVSOP-16 光电二极管 逻辑集成电路 触发器 电视 |
| 文件： | 总22页 (文件大小：1015K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢃ ꢆ ꢇꢈ ꢀꢁꢉ ꢃꢄꢅ ꢃꢆ ꢃꢆ ꢇ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢇꢀ ꢐꢁꢑꢒꢓ ꢔꢁ ꢔꢕ ꢀ ꢍꢎ ꢁꢇꢓꢐ ꢑꢔ ꢕ ꢁꢏ ꢖꢓ ꢀ
SCES226I − APRIL 1999 − REVISED MAY 2005
D
D
D
D
2-V to 5.5-V V
Operation
D
D
D
D
D
Individual Switch Controls
Extremely Low Input Current
CC
Typical V
OLP
(Output Ground Bounce)
= 3.3 V, T = 25°C
<0.8 V at V
CC
A
I
Supports Partial-Power-Down Mode
off
Typical V
>2.3 V at V
(Output V
Undershoot)
Operation
OHV
CC
OH
= 3.3 V, T = 25°C
A
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Support Mixed-Mode Voltage Operation on
All Ports
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
D
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
D
− 1000-V Charged-Device Model (C101)
SN54LV4040A . . . J OR W PACKAGE
SN74LV4040A . . . D, DB, DGV, N, NS,
OR PW PACKAGE
SN74LV4040A . . . RGY PACKAGE
(TOP VIEW)
SN54LV4040A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
16
Q
Q
V
CC
3
2
1
20 19
18
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L
Q
Q
Q
Q
4
5
6
7
8
J
E
15
14
13
12
11
10
Q
Q
2
3
4
5
6
7
Q
Q
Q
Q
CLR
CLK
Q
Q
Q
Q
F
K
J
H
I
F
E
K
J
H
I
17
16
15
14
H
G
Q
Q
E
NC
NC
Q
G
G
Q
I
CLR
Q
D
Q
C
Q
Q
D
Q
D
C
C
Q
CLR
CLK
9 10 11 12 13
Q
B
Q
B
8
9
GND
Q
A
NC − No internal connection
description/ordering information
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 25
SN74LV4040AN
SN74LV4040AN
LW040A
QFN − RGY
Reel of 1000
Tube of 40
SN74LV4040ARGYR
SN74LV4040AD
SOIC − D
LV4040A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV4040ADR
SN74LV4040ANSR
SN74LV4040ADBR
SN74LV4040APW
SN74LV4040APWR
SN74LV4040APWT
SN74LV4040ADGVR
SNJ54LV4040AJ
SOP − NS
74LV4040A
LW040A
−40°C to 85°C
SSOP − DB
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LW040A
TVSOP − DGV
CDIP − J
LW040A
SNJ54LV4040AJ
SNJ54LV4040AW
SNJ54LV4040AFK
CFP − W
Tube of 150
Tube of 55
SNJ54LV4040AW
SNJ54LV4040AFK
−55°C to 125°C
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢕ ꢁ ꢄꢖꢀꢀ ꢔ ꢏꢒ ꢖꢓꢗ ꢎꢀ ꢖ ꢁ ꢔꢏꢖꢘ ꢙꢚ ꢛꢜ ꢝꢞꢟ ꢠꢡꢢ ꢣꢙ ꢟꢞ ꢣꢙꢤ ꢛꢣꢜ ꢥꢓ ꢔ ꢘ ꢕ ꢑꢏ ꢎꢔ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢃꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢅ ꢃ ꢆꢃ ꢆ ꢇ
ꢊꢋ ꢌꢍꢎ ꢏ ꢇ ꢀꢐꢁ ꢑ ꢒ ꢓꢔ ꢁꢔ ꢕꢀ ꢍꢎ ꢁ ꢇꢓꢐ ꢑꢔ ꢕ ꢁꢏ ꢖꢓꢀ
SCES226I − APRIL 1999 − REVISED MAY 2005
description/ordering information (continued)
The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available
externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low.
The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay
circuits, counter controls, and frequency-dividing circuits.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each buffer)
INPUTS
FUNCTION
CLK
↑
CLR
L
No change
Advance to next stage
All outputs L
↓
L
X
H
logic diagram (positive logic)
11
CLR
R
R
R
R
R
10
CLK
T
T
T
T
T
9
7
6
5
3
Q
Q
Q
Q
Q
E
A
B
C
D
R
R
R
R
R
R
R
T
T
T
T
T
T
T
2
4
13
Q
12
14
15
1
Q
Q
Q
Q
Q
Q
L
F
G
H
I
J
K
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢃ ꢆ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢃꢆ ꢃꢆ ꢇ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢇꢀꢐ ꢁꢑꢒꢓ ꢔꢁ ꢔꢕꢀ ꢍꢎ ꢁꢇꢓꢐ ꢑ ꢔꢕ ꢁ ꢏꢖ ꢓꢀ
SCES226I − APRIL 1999 − REVISED MAY 2005
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance or
power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢃꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢅ ꢃ ꢆꢃ ꢆ ꢇ
ꢊꢋ ꢌꢍꢎ ꢏ ꢇ ꢀꢐꢁ ꢑ ꢒ ꢓꢔ ꢁꢔ ꢕꢀ ꢍꢎ ꢁ ꢇꢓꢐ ꢑꢔ ꢕ ꢁꢏ ꢖꢓꢀ
SCES226I − APRIL 1999 − REVISED MAY 2005
recommended operating conditions (see Note 5)
SN54LV4040A
SN74LV4040A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
V
V
V
× 0.3
× 0.3
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
Input voltage
0
0
5.5
0
0
5.5
V
V
I
Output voltage
V
V
O
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV4040A
SN74LV4040A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
2 V to 5.5 V
2.3 V
V
− 0.1
2
V
CC
− 0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
1.9
1.9
i
I
CC
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ꢨ
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ꢠ
ꢝ ꢢ ꢜ ꢛ ꢯ ꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪ ꢞꢨ ꢡꢢ ꢣ ꢙꢫ ꢑ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ
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ꢙ
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ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢙ
ꢞ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢃ ꢆ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢃꢆ ꢃꢆ ꢇ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢇꢀꢐ ꢁꢑꢒꢓ ꢔꢁ ꢔꢕꢀ ꢍꢎ ꢁꢇꢓꢐ ꢑ ꢔꢕ ꢁ ꢏꢖ ꢓꢀ
SCES226I − APRIL 1999 − REVISED MAY 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV4040A SN74LV4040A
A
UNIT
MIN
7
MAX
MIN
7
MAX
MIN
7
MAX
CLK high or low
CLR high
t
t
Pulse duration
Setup time
ns
ns
w
6.5
6.5
6.5
6.5
6.5
6.5
CLR inactive before CLK↓
su
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV4040A SN74LV4040A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLK high or low
CLR high
t
t
Pulse duration
Setup time
ns
ns
w
5
5
5
5
5
5
CLR inactive before CLK↓
su
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV4040A SN74LV4040A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLK high or low
CLR high
t
t
Pulse duration
Setup time
ns
ns
w
5
5
5
5
5
5
CLR inactive before CLK↓
su
switching characteristics over recommended operating free-air temperature range,
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
115*
95
SN54LV4040A SN74LV4040A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
50*
40
MAX
MIN
40*
35
1*
1*
1*
1
MAX
MIN
40
35
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
t
t
8.7* 19.4*
8.7* 19.4*
9.3* 19.9*
23*
23*
24*
28
23
23
24
28
28
28
PLH
PHL
PHL
PLH
PHL
PHL
C
C
= 15 pF
= 15 pF
ns
ns
CLK
CLR
Q
A
L
L
1
1
Any Q
10.5
10.5
11.7
24.1
24.1
24.5
1
C
= 50 pF
ns
CLK
CLR
Q
A
L
1
28
1
C
C
= 50 pF
= 50 pF
1
28
1
ns
ns
Any Q
L
L
∆t
pd
Q
n
1.7
5.9
7
7
Q
n+1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢥ
ꢓ
ꢔ
ꢘ
ꢕ
ꢑ
ꢏ
ꢥ
ꢓ
ꢖ
ꢅ
ꢎ
ꢖ
ꢗ
ꢛ
ꢣ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢧ
ꢣ
ꢜ
ꢨ
ꢧ
ꢞ
ꢝ
ꢠ
ꢝꢢ ꢜ ꢛ ꢯꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪꢞ ꢨꢡꢢ ꢣꢙꢫ ꢑ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ
ꢟ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢰ
ꢢ
ꢞ
ꢧ
ꢜ
ꢨ
ꢢ
ꢟ
ꢛ
ꢦ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢧ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢯ
ꢣ
ꢯ
ꢞ
ꢤ
ꢪ
ꢜ
ꢫ
ꢏ
ꢢ
ꢬ
ꢤ
ꢜ
ꢎ
ꢣ
ꢜ
ꢙ
ꢧ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞꢝ ꢠꢟꢙ ꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ
ꢙ
ꢜ
ꢧ
ꢢ
ꢜ
ꢢ
ꢧ
ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢙ
ꢞ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢃꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢅ ꢃ ꢆꢃ ꢆ ꢇ
ꢊꢋ ꢌꢍꢎ ꢏ ꢇ ꢀꢐꢁ ꢑ ꢒ ꢓꢔ ꢁꢔ ꢕꢀ ꢍꢎ ꢁ ꢇꢓꢐ ꢑꢔ ꢕ ꢁꢏ ꢖꢓꢀ
SCES226I − APRIL 1999 − REVISED MAY 2005
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
SN54LV4040A SN74LV4040A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
75*
55
MAX
MIN
75*
50
1*
1*
1*
1
MAX
MIN
75
50
1
MAX
C
C
= 15 pF
= 50 pF
160*
130
L
L
f
MHz
max
t
t
t
t
t
t
6.1* 11.9*
6.1* 11.9*
7.1* 12.8*
14*
14*
14
14
PLH
PHL
PHL
PLH
PHL
PHL
C
C
= 15 pF
= 15 pF
ns
ns
CLK
CLR
Q
A
L
L
1
15*
1
15
Any Q
7.5
7.5
9
15.4
15.4
16.3
17.5
17.5
18.5
1
17.5
17.5
18.5
C
= 50 pF
ns
CLK
CLR
Q
A
L
1
1
C
C
= 50 pF
= 50 pF
1
1
ns
ns
Any Q
L
L
∆t
pd
Q
n
1.2
4.4
5
5
Q
n+1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
235*
185
4.2*
4.2*
5.3*
5.3
SN54LV4040A SN74LV4040A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
150*
95
MAX
MIN
125*
80
1*
MAX
MIN
125
80
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
t
t
7.3*
7.3*
8.6*
9.3
8.5*
8.5*
10*
8.5
8.5
PLH
PHL
PHL
PLH
PHL
PHL
C
C
= 15 pF
= 15 pF
ns
ns
CLK
CLR
Q
A
L
L
1*
1
1*
1
10
Any Q
1
10.5
10.5
12
1
10.5
10.5
12
C
= 50 pF
ns
CLK
CLR
Q
A
L
5.3
9.3
1
1
C
C
= 50 pF
= 50 pF
6.8
10.6
1
1
ns
ns
Any Q
L
L
∆t
pd
Q
n
0.8
3.1
3.5
3.5
Q
n+1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 6)
CC
L
A
SN74LV4040A
PARAMETER
UNIT
MIN
TYP
0.5
MAX
V
OL(P)
V
OL(V)
V
IH(D)
V
IL(D)
Quiet output, maximum dynamic V
0.8
V
V
V
V
OL
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.5
−0.8
OL
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
11.9
13.1
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
ꢥ
ꢓ
ꢔ
ꢘ
ꢕ
ꢑ
ꢏ
ꢥ
ꢓ
ꢖ
ꢅ
ꢎ
ꢖ
ꢗ
ꢛ
ꢣ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢧ
ꢣ
ꢜ
ꢨ
ꢧ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢯ ꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪ ꢞꢨ ꢡꢢ ꢣ ꢙꢫ ꢑ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢰ
ꢢ
ꢞ
ꢧ
ꢜ
ꢨ
ꢢ
ꢟ
ꢛ
ꢦ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢧ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢯ
ꢣ
ꢯ
ꢞ
ꢤ
ꢪ
ꢜ
ꢫ
ꢏ
ꢢ
ꢬ
ꢤ
ꢜ
ꢎ
ꢣ
ꢜ
ꢙ
ꢧ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚ ꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞ ꢝꢠꢟ ꢙꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ
ꢙ
ꢜ
ꢧ
ꢢ
ꢜ
ꢢ
ꢧ
ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢙ
ꢞ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢃ ꢆ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢃꢆ ꢃꢆ ꢇ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢇꢀꢐ ꢁꢑꢒꢓ ꢔꢁ ꢔꢕꢀ ꢍꢎ ꢁꢇꢓꢐ ꢑ ꢔꢕ ꢁ ꢏꢖ ꢓꢀ
SCES226I − APRIL 1999 − REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
CC
V
CC
Output
Control
50% V
CC
50% V
CC
50% V
CC
50% V
t
CC
0 V
0 V
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
OL
+ 0.3 V
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2009
PACKAGING INFORMATION
Orderable Device
SN74LV4040AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4040ADBR
SN74LV4040ADBRE4
SN74LV4040ADBRG4
SN74LV4040ADE4
SN74LV4040ADG4
SN74LV4040ADGVR
SN74LV4040ADGVRE4
SN74LV4040ADGVRG4
SN74LV4040ADR
SSOP
SSOP
SSOP
SOIC
DB
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
TVSOP
SOIC
DGV
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4040ADRE4
SN74LV4040ADRG4
SN74LV4040AN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74LV4040ANE4
SN74LV4040ANSR
SN74LV4040ANSRE4
SN74LV4040ANSRG4
SN74LV4040APW
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SO
NS
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4040APWE4
SN74LV4040APWG4
SN74LV4040APWR
SN74LV4040APWRE4
SN74LV4040APWRG4
SN74LV4040APWT
SN74LV4040APWTE4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2009
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74LV4040APWTG4
SN74LV4040ARGYR
SN74LV4040ARGYRG4
TSSOP
PW
16
16
16
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
VQFN
VQFN
RGY
RGY
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4040A :
Enhanced Product: SN74LV4040A-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV4040ADBR
SN74LV4040ADGVR
SN74LV4040ADR
SSOP
TVSOP
SOIC
DB
DGV
D
16
16
16
16
16
16
16
2000
2000
2500
2000
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
16.4
12.4
12.4
12.4
8.2
6.8
6.5
8.2
6.9
6.9
3.8
6.6
4.0
2.5
1.6
2.1
2.5
1.6
1.6
1.5
12.0
8.0
16.0
12.0
16.0
16.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
10.3
10.5
5.6
8.0
SN74LV4040ANSR
SN74LV4040APWR
SN74LV4040APWT
SN74LV4040ARGYR
SO
NS
12.0
8.0
TSSOP
TSSOP
VQFN
PW
PW
RGY
5.6
8.0
3000
4.3
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV4040ADBR
SN74LV4040ADGVR
SN74LV4040ADR
SSOP
TVSOP
SOIC
DB
DGV
D
16
16
16
16
16
16
16
2000
2000
2500
2000
2000
250
367.0
367.0
333.2
367.0
367.0
367.0
367.0
367.0
367.0
345.9
367.0
367.0
367.0
367.0
38.0
35.0
28.6
38.0
35.0
35.0
35.0
SN74LV4040ANSR
SN74LV4040APWR
SN74LV4040APWT
SN74LV4040ARGYR
SO
NS
TSSOP
TSSOP
VQFN
PW
PW
RGY
3000
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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