概述
规格参数
数据手册
替代型号SN74LVC07APWRG3 概述
HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS HEX缓冲器/驱动器，具有漏极开路输出 逻辑控制器 栅极
SN74LVC07APWRG3 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | TSSOP |
| 包装说明： | TSSOP, TSSOP14,.25 | 针数： | 14 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 1 week |
| 风险等级： | 0.68 | 系列： | LVC/LCX/Z |
| JESD-30 代码： | R-PDSO-G14 | JESD-609代码： | e3 |
| 长度： | 5 mm | 负载电容（CL）： | 50 pF |
| 逻辑集成电路类型： | BUFFER | 最大I（ol）： | 0.024 A |
| 湿度敏感等级： | 1 | 功能数量： | 6 |
| 输入次数： | 1 | 端子数量： | 14 |
| 最高工作温度： | 125 °C | 最低工作温度： | -40 °C |
| 输出特性： | OPEN-DRAIN | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | TSSOP | 封装等效代码： | TSSOP14,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| 包装方法： | TR | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 3.3 V | 最大电源电流（ICC）： | 0.01 mA |
| Prop。Delay @ Nom-Sup： | 3.6 ns | 传播延迟（tpd）： | 5.6 ns |
| 认证状态： | Not Qualified | 施密特触发器： | NO |
| 座面最大高度： | 1.2 mm | 子类别： | Gates |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 1.65 V |
| 标称供电电压 (Vsup)： | 1.8 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | AUTOMOTIVE |
| 端子面层： | Matte Tin (Sn) | 端子形式： | GULL WING |
| 端子节距： | 0.65 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 4.4 mm |
| Base Number Matches： | 1 |
SN74LVC07APWRG3 数据手册
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PDF下载SN74LVC07A
www.ti.com.................................................................................................................................................... SCAS595R–OCTOBER 1997–REVISED APRIL 2008
HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
1
FEATURES
•
Operates From 1.65 V to 5 V
•
•
Max tpd of 2.6 ns at 5 V
•
Inputs and Open-Drain Outputs Accept
Voltages up to 5.5 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
DESCRIPTION/ORDERING INFORMATION
This hex buffer/driver is designed for 1.65-V to 5.5-V VCC operation.
The outputs of the SN74LVC07A device are open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of
this device as translators in a mixed-system environment.
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
SN74LVC07ARGYR
SN74LVC07AD
TOP-SIDE MARKING
LC07A
QFN – RGY
SOIC – D
Reel of 1000
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
SN74LVC07ADR
LVC07A
SN74LVC07ADT
SOP – NS
SN74LVC07ANSR
SN74LVC07ADBR
SN74LVC07APW
LVC07A
LC07A
–40°C to 85°C
SSOP – DB
TSSOP – PW
TVSOP – DGV
Reel of 2000
Reel of 250
Reel of 2000
SN74LVC07APWR
SN74LVC07APWT
SN74LVC07ADGVR
LC07A
LC07A
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC07A
SCAS595R–OCTOBER 1997–REVISED APRIL 2008.................................................................................................................................................... www.ti.com
FUNCTION TABLE
(EACH BUFFER/DRIVER)
INPUT
A
OUTPUT
Y
H
L
H
L
LOGIC DIAGRAM, EACH BUFFER/DRIVER (POSITIVE LOGIC)
A
Y
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
6.5
V
VO
IIK
Output voltage range
6.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
86
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
D package(3)
DB package
(3)
96
DGV package(3)
NS package(3)
PW package(3)
RGY package(4)
127
76
θJA
Package thermal impedance
Storage temperature range
°C/W
°C
113
47
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) The package thermal impedance is calculated in accordance with JESD 51-5.
2
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Copyright © 1997–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A
SN74LVC07A
www.ti.com.................................................................................................................................................... SCAS595R–OCTOBER 1997–REVISED APRIL 2008
RECOMMENDED OPERATING CONDITIONS(1)
MIN
1.65
MAX
UNIT
VCC
Supply voltage
5.5
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65 × VCC
1.7
VIH
High-level input voltage
V
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
0.8
0.3 × VCC
VI
Input voltage
0
0
5.5
5.5
4
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
12
24
24
85
IOL
Low-level output current
mA
VCC = 4.5 V
TA
Operating free-air temperature
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
2.3 V
MIN
TYP(1)
MAX
0.2
UNIT
IOL = 100 µA
IOL = 4 mA
0.45
0.7
VOL
V
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3 V
0.55
±5
II
VI = 5.5 V or GND
VI or VO = 5.5 V
VI = VCC or GND,
3.6 V
µA
µA
µA
Ioff
ICC
0 V
±10
10
IO = 0
3.6 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
ΔICC
2.7 V to 3.6 V
3.3 V
500
µA
Ci
VI = VCC or GND
5
pF
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Copyright © 1997–2008, Texas Instruments Incorporated
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SN74LVC07A
SCAS595R–OCTOBER 1997–REVISED APRIL 2008.................................................................................................................................................... www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 4)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
3.3
MIN
MAX
3.6
MIN
MAX
2.6
tpd
A
Y
1
5.6
1
3.4
1
1
ns
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
VCC = 5 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
Power dissipation capacitance
per buffer/driver
Cpd
f = 10 MHz
1.8
2
2.5
3.78
pF
4
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Copyright © 1997–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A
SN74LVC07A
www.ti.com.................................................................................................................................................... SCAS595R–OCTOBER 1997–REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × V
CC
S1
Open
GND
1 kΩ
From Output
Under Test
TEST
S1
2 × V
2 × V
2 × V
t
(see Note F)
(see Note G)
PZL
CC
CC
CC
C = 30 pF
(see Note A)
L
1 kΩ
t
PLZ
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
V
CC
V
V
CC
V
CC
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
S1 at 2 × V
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t and t are the same as t
.
pd
PLZ
PZL
F.
G.
t
t
is measured at V /2.
CC
is measured at V + 0.15 V.
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 1997–2008, Texas Instruments Incorporated
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Product Folder Link(s): SN74LVC07A
SN74LVC07A
SCAS595R–OCTOBER 1997–REVISED APRIL 2008.................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
2 × V
2 × V
2 × V
t
(see Note F)
(see Note G)
PZL
CC
CC
CC
C = 30 pF
(see Note A)
L
500 Ω
t
PLZ
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
V
CC
V
V
CC
V
CC
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
S1 at 2 × V
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t and t are the same as t
.
pd
PLZ
PZL
F.
G.
t
t
is measured at V /2.
CC
is measured at V + 0.15 V.
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
6
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Copyright © 1997–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A
SN74LVC07A
www.ti.com.................................................................................................................................................... SCAS595R–OCTOBER 1997–REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 and 3.3 V ± 0.3 V
6 V
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
6 V
6 V
6 V
t
(see Note F)
(see Note G)
PZL
C = 50 pF
(see Note A)
L
t
PLZ
500 Ω
t
/t
PHZ PZH
LOAD CIRCUIT
1.5 V
t
w
2.7 V
0 V
2.7 V
0 V
1.5 V
1.5 V
Input
Timing
Input
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Output
Control
(low-level
enabling)
Data
Input
2.7 V
0 V
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
OL
+ 0.3 V
V
OL
(see Note B)
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at 6 V
3 V
0 V
3 V
2.7 V
1.5 V
Output
1.5 V
1.5 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t and t are the same as t
.
pd
PLZ
PZL
F.
G.
t
t
is measured at 1.5 V.
is measured at V + 0.3 V.
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
Copyright © 1997–2008, Texas Instruments Incorporated
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Product Folder Link(s): SN74LVC07A
SN74LVC07A
SCAS595R–OCTOBER 1997–REVISED APRIL 2008.................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC = 5 V ± 0.5 V
2 x V
CC
500 Ω
2 x V
CC
2 x V
CC
500 Ω
2 x V
CC
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at 2 x V
CC
0.3 V
(see Note B)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal connections such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal connections such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t and t are the same as t
.
pd
PLZ
PZL
F. t
G. t
is measured at V /2.
PZL
PLZ
CC
is measured at V + 0.3 V.
OL
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
8
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Copyright © 1997–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A
PACKAGE OPTION ADDENDUM
www.ti.com
9-Apr-2010
PACKAGING INFORMATION
Orderable Device
SN74LVC07AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC07ADBR
SN74LVC07ADBRG4
SN74LVC07ADE4
SN74LVC07ADG4
SN74LVC07ADGVR
SN74LVC07ADGVRE4
SN74LVC07ADGVRG4
SN74LVC07ADR
SSOP
SSOP
SOIC
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
TVSOP
SOIC
DGV
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC07ADRE4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC07ADRG3
SN74LVC07ADRG4
PREVIEW
ACTIVE
SOIC
SOIC
D
D
14
14
2500
TBD
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2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC07ADT
SN74LVC07ADTE4
SN74LVC07ADTG4
SN74LVC07ANSR
SN74LVC07ANSRE4
SN74LVC07ANSRG4
SN74LVC07APW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SO
D
14
14
14
14
14
14
14
14
14
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
NS
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC07APWE4
SN74LVC07APWG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC07APWLE
SN74LVC07APWR
OBSOLETE TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC07APWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC07APWRG3
SN74LVC07APWRG4
PREVIEW
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
2000
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Apr-2010
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74LVC07APWT
SN74LVC07APWTE4
SN74LVC07APWTG4
SN74LVC07ARGYR
SN74LVC07ARGYRG4
TSSOP
PW
14
14
14
14
14
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
VQFN
PW
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
RGY
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC07A :
Automotive: SN74LVC07A-Q1
Enhanced Product: SN74LVC07A-EP
•
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC07ADBR
SN74LVC07ADGVR
SN74LVC07ADR
SN74LVC07ADR
SN74LVC07ADT
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
14
14
14
14
2000
2000
2500
2500
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
16.4
16.4
16.4
12.4
12.4
12.4
8.2
6.8
6.5
6.5
6.5
8.2
6.9
6.9
3.75
6.6
4.0
2.5
1.6
2.1
2.1
2.1
2.5
1.6
1.6
1.15
12.0
8.0
8.0
8.0
8.0
12.0
8.0
8.0
8.0
16.0
12.0
16.0
16.0
16.0
16.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
9.0
SOIC
D
9.0
SOIC
D
9.0
SN74LVC07ANSR
SN74LVC07APWR
SN74LVC07APWT
SN74LVC07ARGYR
SO
NS
PW
PW
RGY
2000
2000
250
10.5
5.6
TSSOP
TSSOP
VQFN
5.6
3000
3.75
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC07ADBR
SN74LVC07ADGVR
SN74LVC07ADR
SN74LVC07ADR
SN74LVC07ADT
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
14
14
14
14
2000
2000
2500
2500
250
346.0
346.0
346.0
333.2
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
345.9
346.0
346.0
346.0
346.0
346.0
33.0
29.0
33.0
28.6
33.0
33.0
29.0
29.0
29.0
SOIC
D
SOIC
D
SN74LVC07ANSR
SN74LVC07APWR
SN74LVC07APWT
SN74LVC07ARGYR
SO
NS
PW
PW
RGY
2000
2000
250
TSSOP
TSSOP
VQFN
3000
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74LVC07APWRG3 CAD模型
引脚图
封装焊盘图
SN74LVC07APWRG3 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| SN74LVC07APWTE4 | TI | HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS | 完全替代 |
|
| SN74LVC07APWR | TI | HEX BUFFERS DRIVERS WITH OPEN-DRAIN OUTPUTS | 完全替代 |
|
| SN74LVC07APWG4 | TI | HEX BUFFERS DRIVERS WITH OPEN-DRAIN OUTPUTS | 完全替代 |
|
SN74LVC07APWRG3 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| SN74LVC07APWRG4 | TI | HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS | 获取价格 |
|
| SN74LVC07APWT | TI | HEX BUFFERS DRIVERS WITH OPEN-DRAIN OUTPUTS | 获取价格 |
|
| SN74LVC07APWTE4 | TI | HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS | 获取价格 |
|
| SN74LVC07APWTG4 | TI | HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS | 获取价格 |
|
| SN74LVC07AQDRQ | TI | HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS | 获取价格 |
|
| SN74LVC07AQPWRG4Q1 | TI | 具有漏极开路输出的汽车类 6 通道、1.65V 至 5.5V 缓冲器 | PW | 14 | -40 to 125 | 获取价格 |
|
| SN74LVC07AQPWRQ | TI | HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS | 获取价格 |
|
| SN74LVC07AQPWRQ1 | TI | 具有漏极开路输出的汽车类 6 通道、1.65V 至 5.5V 缓冲器 | PW | 14 | -40 to 125 | 获取价格 |
|
| SN74LVC07ARGYR | TI | HEX BUFFERS DRIVERS WITH OPEN-DRAIN OUTPUTS | 获取价格 |
|
| SN74LVC07ARGYRG4 | TI | HEX BUFFERS DRIVERS WITH OPEN-DRAIN OUTPUTS | 获取价格 |
|
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