SN74LVC1G74RSE2 [TI]
具有清零和预置端的单路正边沿触发式 D 型触发器 | RSE | 8 | -40 to 125;
| 型号： | SN74LVC1G74RSE2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有清零和预置端的单路正边沿触发式 D 型触发器 | RSE | 8 | -40 to 125 触发器 锁存器 |
| 文件： | 总19页 (文件大小：720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G74
www.ti.com
SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
Check for Samples: SN74LVC1G74
1
FEATURES
2
•
Available in the Texas Instruments NanoFree™
Package
•
•
•
Ioff Supports Live Insertion, Partial Power
Down Mode, and Back Drive Protection
•
•
•
•
•
•
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.9 ns at 3.3 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
1000-V Charged-Device Model (C101)
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(TOP VIEW)
A1
B1
C1
D1
A2
B2
C2
D2
1 8
2 7
3 6
4 5
VCC
PRE
CLR
Q
VCC
1
2
3
4
8
7
6
5
CLK
D
CLK
D
Q
GND
VCC
1
2
3
4
8
7
6
5
CLK
D
PRE
CLR
Q
PRE
CLR
Q
Q
GND
Q
GND
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
SN74LVC1G74
SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012
www.ti.com
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING(3)
TA
PACKAGE(1) (2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
–40°C to 85°C
Reel of 3000
Reel of 3000
SN74LVC1G74YZPR
_ _ _DP_
SN74LVC1G74DCTR
SN74LVC1G74DCUR
SN74LVC1G74DCURG4
SN74LVC1G74DCUT
N74_ _ _
N74_
–40°C to 125°C
Reel of 3000
Reel of 250
VSSOP – DCU
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
D
X
X
X
H
L
Q
H
Q
L
H
L
X
L
H(1)
H
H(1)
L
L
X
H
H
↑
H
L
H
H
↑
L
H
H
H
L
X
Q0
Q 0
(1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
LOGIC DIAGRAM (POSITIVE LOGIC)
7
1
PRE
CLK
C
C
C
5
Q
TG
C
C
C
C
2
6
D
TG
TG
TG
3
Q
C
C
C
CLR
2
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Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G74
SN74LVC1G74
www.ti.com
SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC Supply voltage range
6.5
6.5
6.5
V
V
VI
Input voltage range(2)
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2) (3)
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
VO < 0
–50
–50
mA
mA
mA
mA
IOK
IO
Output clamp current
Continuous output current
Continuous current through VCC or GND
±50
±100
220
DCT package
DCU package
YZP package
θJA
Package thermal impedance(4)
227 °C/W
102
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright © 2009–2012, Texas Instruments Incorporated
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SN74LVC1G74
SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012
www.ti.com
RECOMMENDED OPERATING CONDITIONS(1)
MIN
1.65
MAX UNIT
Operating
5.5
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
0.3 × VCC
5.5
VCC
–4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–32
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
YZP Package
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
5
–40
–40
85
TA
DCT Package
°C
125
DCU Package
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Product Folder Link(s): SN74LVC1G74
SN74LVC1G74
www.ti.com
SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN TYP(1)
VCC – 0.1
MAX UNIT
IOH = –100 μA
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 μA
IOL = 4 mA
1.2
1.9
2.4
2.3
3.8
2.3 V
VOH
V
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
IOL = 8 mA
2.3 V
0.3
V
VOL
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
0.4
3 V
0.55
0.55
4.5 V
Data or
control inputs
II
VI = 5.5 V or GND
0 to 5.5 V
±5
μA
Ioff
VI or VO = 5.5 V
0
±10
10
μA
μA
μA
pF
ICC
VI = 5.5 V or GND,
IO = 0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
ΔICC
One input at VCC – 0.6 V, Other inputs at VCC or GND
500
Ci
VI = VCC or GND
5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
85°C
125°C
Parame
ter
From
To
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
fclock
tw
80
175
175
200
175
200 MHz
CLK
6.2
6.2
2.9
1.9
0
2.7
2.7
1.7
1.4
0.3
2.7
2.7
1.3
1.2
1.2
2
2
2.7
2.7
1.3
1.2
1.2
2
2
ns
PRE or CLR low
Data
1.1
1
1.1
1.2
0.5
tsu
th
ns
ns
PRE or CLR inactive
0.5
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
85°C
125°C
VCC = 3.3 V VCC = 5 V
Parame
ter
From
To
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
VCC = 5 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
fmax
80
175
2.2
3
175
2.2
2.6
1.7
200
1.4
1.6
1.6
175
2.2
2.6
1.7
200
1.4
1.6
1.6
MHz
Q
Q
4.8 13.4
7.1
7.7
7
5.9
6.2
5.9
4.1
4.4
4.1
7.9
8.2
7.9
6.1
CLK
tpd
6
14.4
6.4 ns
6.1
PRE or CLR low
Q or Q
4.4 12.9
2.3
Copyright © 2009–2012, Texas Instruments Incorporated
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SN74LVC1G74
SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012
www.ti.com
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
VCC = 5 V
TYP
PARAMETER
TEST CONDITIONS
f = 10 MHz
UNIT
Cpd
Power dissipation capacitance
35
35
37
40
pF
6
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Product Folder Link(s): SN74LVC1G74
SN74LVC1G74
www.ti.com
SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012
PARAMETER MEASUREMENT INFORMATION
VLOAD
Open
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
GND
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2009–2012, Texas Instruments Incorporated
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SN74LVC1G74
SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012
www.ti.com
REVISION HISTORY
Changes from Original (October 2009) to Revision A
Page
•
•
•
•
Changed Ioff description in FEATURES. ............................................................................................................................... 1
Changed temperature range for DCT and DCU package from (–40°C to 85°C) to (–40°C to 125°). .................................. 2
Changed TIMING REQUIREMENTS table. .......................................................................................................................... 5
Changed SWITCHING CHARACTERISTICS table. ............................................................................................................. 5
Changes from Revision A (November 2011) to Revision B
Page
•
Added SN74LVC1G74DCURG4 part number to ORDERING INFORMATION table. ......................................................... 2
8
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Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G74
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LVC1G74DCT3
SN74LVC1G74DCTR
PREVIEW
ACTIVE
SM8
SM8
DCT
DCT
8
8
250
TBD
Call TI
Call TI
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G74DCTRE6
SN74LVC1G74DCU
SN74LVC1G74DCU6
PREVIEW
PREVIEW
PREVIEW
SM8
US8
US8
DCT
DCU
DCU
8
8
8
3000
3000
3000
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G74DCUR
SN74LVC1G74DCURG4
SN74LVC1G74DCUT
ACTIVE
ACTIVE
ACTIVE
US8
US8
US8
DCU
DCU
DCU
8
8
8
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74LVC1G74YZPR
SN74LVC1G74YZTR
PREVIEW
PREVIEW
DSBGA
DSBGA
YZP
YZT
8
8
3000
3000
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2012
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G74DCTR
SN74LVC1G74DCUR
SN74LVC1G74DCURG4
SN74LVC1G74DCUT
SM8
US8
US8
US8
DCT
DCU
DCU
DCU
8
8
8
8
3000
3000
3000
250
180.0
180.0
180.0
180.0
13.0
8.4
8.4
8.4
3.35
2.25
2.25
2.25
4.5
1.55
1.05
1.05
1.05
4.0
4.0
4.0
4.0
12.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
3.35
3.35
3.35
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC1G74DCTR
SN74LVC1G74DCUR
SN74LVC1G74DCURG4
SN74LVC1G74DCUT
SM8
US8
US8
US8
DCT
DCU
DCU
DCU
8
8
8
8
3000
3000
3000
250
182.0
202.0
202.0
202.0
182.0
201.0
201.0
201.0
20.0
28.0
28.0
28.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
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